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PDF ( 数据手册 , 数据表 ) 9FGV0631C

零件编号 9FGV0631C
描述 6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator
制造商 IDT
LOGO IDT LOGO 


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9FGV0631C 数据手册, 描述, 功能
6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator 9FGV0631C
DATASHEET
General Description
The 9FGV0631C is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power PCIe clock family. The device has 6 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off and 2 selectable SMBus
addresses.
Recommended Application
1.8V PCIe Gen 1-2-3 Clock Generator
Output Features
6 - 100MHz Low-Power (LP) HCSL DIF pairs
1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 Compliant
REF phase jitter is <1.5ps RMS
Block Diagram
Features/Benefits
LP-HCSL outputs; save 12 resistors compared to standard
PCIe devices
54mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 40-pin 5x5 mm VFQFPN; minimal board
space
vOE(5:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0631C OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.







9FGV0631C pdf, 数据表
9FGV0631C DATASHEET
Electrical Characteristics–REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Tperiod
25 MHz output
Rise/Fall Slew Rate
trf1
Byte 3 = 1F, 20% to 80% of VDDREF
0.6
Rise/Fall Slew Rate
trf1
Byte 3 = 5F, 20% to 80% of VDDREF
0.9
Rise/Fall Slew Rate
trf1
Byte 3 = 9F, 20% to 80% of VDDREF
1.1
Rise/Fall Slew Rate
trf1
Byte 3 = DF, 20% to 80% of VDDREF
1.1
Duty Cycle
dt1X
VT = VDD/2 V
45
Duty Cycle Distortion
dtcd
VT = VDD/2 V
0
Jitter, cycle to cycle
tjcyc-cyc
VT = VDD/2 V
Noise floor
tjdBc1k
1kHz offset
Noise floor
tjdBc10k
10kHz offset to Nyquist
TYP
0
40
1
1.4
1.7
1.8
49.1
2
19.1
-129.8
-143.6
MAX
1.6
2.2
2.7
2.9
55
4
250
-105
-115
Jitter, phase
tjphREF
12kHz to 5MHz
0.63 1.5
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3 Default SMBus Value
4 When driven by a crystal.
5 When driven by an external oscillator via the X1 pin, X2 should be floating.
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
%
ps
dBc
dBc
ps
(rms)
Notes
1,2
2
1
1,3
1
1
1,4
1,5
1,4
1,4
1,4
1,4
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
DIF
Center
Freq.
MHz
100.00
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
-SSC
- ppm
AbsPer Short-Term Long-Term
Min Average Average
Min Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94900
9.99900 10.00000 10.00100
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100 ns 1,2
Clock Periods–Differential Outputs with Spread Spectrum Enabled
SSC ON
DIF
Center
Freq.
MHz
99.75
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
-SSC
- ppm
AbsPer Short-Term Long-Term
Min
Average
Min
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94906 9.99906 10.02406 10.02506 10.02607
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107 ns 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
Clock Periods–Single-ended Outputs
SSC OFF
Center
Freq.
MHz
1 Clock
1us
Measurement Window
0.1s
0.1s
0.1s
-SSC
- ppm
-c2c jitter Short-Term Long-Term
AbsPer Average Average
Min Min
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
REF
25.000 39.79880
39.99880 40.00000 40.00120
1us 1 Clock
+SSC
Short-Term
Average
Max
+c2c jitter Units Notes
AbsPer
Max
40.20120 ns 1,2
6-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR
8
OCTOBER 18, 2016














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