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PDF ( 数据手册 , 数据表 ) 9FGU0831

零件编号 9FGU0831
描述 8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator
制造商 IDT
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9FGU0831 数据手册, 描述, 功能
8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator 9FGU0831
DATASHEET
General Description
The 9FGU0831 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 8 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
Output Features
8 - 100MHz Low-Power (LP) HCSL DIF pairs
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specification
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 60ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Functional Block Diagram
Features/Benefits
LP-HCSL outputs; save 16 resistors compared to standard
PCIe devices
50mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line length
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EM
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGU0831 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.







9FGU0831 pdf, 数据表
9FGU0831 DATASHEET
Electrical Characteristics – DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
1.1 2.2 3.3 V/ns 1,2,3
0.9 1.7 2.6 V/ns 1,2,3
3 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 600 735 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 -16 150
7
7
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Vmax
Vmin
Vswing
Vcross_abs
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
779 1150
-300 -45
mV
7
7
300 1503
mV 1,2,7
250 405 550 mV 1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
12 140 mV 1,6,7
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus amplitude settings.
Electrical Characteristics – DIF Output Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
tjphPCIeG1
Phase Jitter, PLL Mode
tjphPCIeG2
tjphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
27.7
1.0
1.9
0.4
MAX
40
1.3
2.2
0.6
IND.
LIMIT
86
3
3.1
1
UNITS Notes
ps (p-p) 1,2,3,5
ps 1,2,3,5
(rms)
ps 1,2,3,5
(rms)
ps 1,2,3,5
(rms)
tjphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.4 0.6
1 Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Calculated from Intel-supplied Clock Jitter Tool
5 Applies to all differential outputs
0.7
ps
(rms) 1,2,3,5
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
8
OCTOBER 18, 2016







9FGU0831 equivalent, schematic
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
Sales
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
Tech Support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.










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