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PDF ( 数据手册 , 数据表 ) 9FGU0241

零件编号 9FGU0241
描述 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
制造商 IDT
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9FGU0241 数据手册, 描述, 功能
2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0241
DATASHEET
Description
The 9FGU0241 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 2 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
2 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
23mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
vOE(1:0)#
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF1
DIF0
9FGU0241 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.







9FGU0241 pdf, 数据表
9FGU0241 DATASHEET
Electrical Characteristics–REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Duty Cycle
Tperiod
trf1
trf1
trf1
trf1
dt1X
25 MHz output
Byte 3 = 1F, 20% to 80% of VDDREF
Byte 3 = 5F, 20% to 80% of VDDREF
Byte 3 = 9F, 20% to 80% of VDDREF
Byte 3 = DF, 20% to 80% of VDDREF
VT = VDD/2 V
0.3
0.5
0.77
0.84
45
Duty Cycle Distortion
dtcd VT = VDD/2 V, when driven by XIN/CLKIN_25 pin 0
Jitter, cycle to cycle
Noise floor
Noise floor
tjcyc-cyc
tjdBc1k
tjdBc10k
VT = VDD/2 V
1kHz offset
10kHz offset to Nyquist
TYP
0
40
0.7
1.0
1.3
1.4
47.1
2.0
51.2
-126
-139
MAX
1.1
1.6
1.9
2.0
55
4
250
-105
-110
Jitter, phase
tjphREF
12kHz to 5MHz
1.11 3
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3 Default SMBus Value
4 When driven by a crystal.
5 X2 should be floating.
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
%
ps
dBc
dBc
ps
(rms)
Notes
1,2
2
1
1,3
1
1
1,4
1,5
1,4
1,4
1,4
1,4
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
DIF
Center
Freq.
MHz
100.00
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94900
9.99900 10.00000 10.00100
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100 ns 1,2
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
SSC ON
DIF
Center
Freq.
MHz
99.75
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94906 9.99906 10.02406 10.02506 10.02607
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107 ns 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
8
OCTOBER 18, 2016














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