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PDF ( 数据手册 , 数据表 ) 9FG1901H

零件编号 9FG1901H
描述 Frequency Generator
制造商 IDT
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9FG1901H 数据手册, 描述, 功能
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
DATASHEET
9FG1901H
Description
Features/Benefits
The 9FG1901H follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H
can provide outputs up to 400MHz.
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Key Specifications
• VDDA controlled power down mode
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
OE(16:5)#, 13
OE_01234#
CLK_IN
CLK_IN#
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(18:17)
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(16:0)
IREF
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1
1386A - 02/02/10







9FG1901H pdf, 数据表
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
SMBusTable: FSB Frequency Select Register
Byte 0 Pin #
Name
Control Function
Bit 7 DIF(16:0)
GRSEL_17
Group of 17 gear ratio select
Bit 6 DIF(18:17)
GRSEL_2
Group of 2 gear ratio select
Bit 5
Reserved
Bit 4
-
FS_A_410 Latched Input
Bit 3
-
FSBG_3
FSB Gear Ratio FS_3
Bit 2
-
FSBG_2
FSB Gear Ratio FS_2
Bit 1
-
FSBG_1
FSB Gear Ratio FS_1
Bit 0
-
FSBG_0
FSB Gear Ratio FS_0
Type
0
RW Gear Ratio
RW Gear Ratio
1
1:1
1:1
RW
RW See ICS9FG1901
RW Programmable Gear Ratios
RW Table
RW
PWD
1
1
X
Latch
x
0
x
1
SMBusTable: Output Control Register
Byte 1 Pin #
Name
Bit 7
DIF_7
Bit 6
DIF_6
Bit 5
DIF_5
Bit 4
DIF_4
Bit 3
DIF_3
Bit 2
DIF_2
Bit 1
DIF_1
Bit 0
DIF_0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBusTable: Output and PLL BW Control Register
Byte 2 Pin #
Name
Control Function
Type
0
Bit 7 see note
PLL_BW# adjust
RW High BW
Bit 6 see note
BYPASS# test mode / PLL
RW Bypass
Bit 5
DIF_13
Output Control
RW Hi-Z
Bit 4
DIF_12
Output Control
RW Hi-Z
Bit 3
DIF_11
Output Control
RW Hi-Z
Bit 2
DIF_10
Output Control
RW Hi-Z
Bit 1
DIF_9
Output Control
RW Hi-Z
Bit 0
DIF_8
Output Control
RW Hi-Z
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
1
Low BW
PLL
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBusTable: Output Enable Readback Register
Byte 3 Pin #
Name
Control Function
Bit 7
Readback - OE9# Input
Bit 6
Readback - OE8# Input
Bit 5
Readback - OE7# Input
Bit 4
Readback - OE6# Input
Bit 3
Readback - OE5# Input
Bit 2
Readback - OE_01234# Input
Bit 1
8
Readback - HIGH_BW# In
Bit 0
72
Readback - SMB_A2_PLLBYP# In
Type
R
R
R
R
R
R
R
R
01
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
PWD
X
X
X
X
X
X
X
X
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
8
1386A - 02/02/10







9FG1901H equivalent, schematic
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v 0.22v 1.08
33
150 100 100
0.58 0.28 0.6
33
78.7 137
100
0.80 0.40 0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60 0.3 1.2 33
174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L1 L2
R1a
R3
L4
L4'
L1' L2'
HCSL Output Buffer
R1b
R2a
R2b
L3' L3
R4
Down Device
REF_CLK Input
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc 0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a R5b
Cc
L4
L4'
Cc
R6a R6b
PCIe Device
REF_CLK Input
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
16
1386A - 02/02/10










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