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PDF ( 数据手册 , 数据表 ) 8SLVP2106

零件编号 8SLVP2106
描述 LVPECL Output Fanout Buffer
制造商 IDT
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8SLVP2106 数据手册, 描述, 功能
Low Phase Noise, Dual 1-to-6, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2106
DATA SHEET
General Description
The 8SLVP2106 is a high-performance differential dual 1:6 LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2106 is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2106 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
Two independent buffers with six low skew outputs each are
available. The integrated bias voltage references enable easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QA5
nQA5
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
QB5
nQB5
Features
Two 1:6, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL, CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 340ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: VCC = 3.3V)
Full 3.3V and 2.5V supply voltage modes
Maximum device current consumption (IEE): 114mA
Available in Lead-free (RoHS 6), 40-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Pin Assignment
30 29 28 27 26 25 24 23 22 21
VCC 31
QB2 32
nQB2 33
QB3 34
nQB3 35
QB4 36
nQB4 37
QB5 38
nQB5 39
VCC 40
8SLVP2106i
40-lead VFQFN
6mm x 6mm x 0.925mm package body
NL Package
Top View
1 2 3 4 5 6 7 8 9 10
20 VCC
19 nQA3
18 QA3
17 nQA2
16 QA2
15 nQA1
14 QA1
13 nQA0
12 QA0
11 VCC
8SLVP2106 REVISION B 6/9/15
1 ©2015 Integrated Device Technology, Inc.







8SLVP2106 pdf, 数据表
8SLVP2106 DATA SHEET
Parameter Measurement Information
2V
SCOPE
VCC Qx
nQx
VEE
-1.3V±0.165V
3.3V LVPECL Output Load Test Circuit
2V
SCOPE
VCC
Qx
nQx
VEE
-0.5V±0.125
2.5V LVPECL Output Load Test Circuit
VCC
nPCLKA,
nPCLKB
PCLKA,
PCLKB
VEE
Differential Input Level
Part 1
nQx
Qx
Part 2
nQy
Qy
t sk(pp)
Part-to-Part Skew
nQx
Qx
nQy
Qy
Output Skew
nQx
Qx
nQy
Qy
t PLH
tsk(p)= |tPHL - tPLH|
t PHL
Pulse Skew
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8
REVISION B 6/9/15







8SLVP2106 equivalent, schematic
8SLVP2106 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8SLVP2106.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8SLVP2106 is the sum of the core power plus the power dissipated at the output(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 114mA = 395mW
• Power (outputs)MAX = 37.1mW/Loaded Output pair
If all outputs are loaded, the total power is 12 * 37.1mW = 445.2mW
Total PowerMAX (3.465V, with all outputs switching) = 395mW + 445.2mW = 840mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 38.1°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.840W * 38.1°C/W = 117°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 5. Thermal Resistance JA for 40-Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
38.1°C/W
1
32°C/W
2
29.9°C/W
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
16
REVISION B 6/9/15










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