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PDF ( 数据手册 , 数据表 ) 8SLVP2104

零件编号 8SLVP2104
描述 LVPECL Output Fanout Buffer
制造商 IDT
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8SLVP2104 数据手册, 描述, 功能
Low Phase Noise, Dual 1-to-4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2104
DATA SHEET
General Description
The 8SLVP2104I is a high-performance differential dual LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2104I is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2104I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
Two 1:4, low skew, low additive jitter LVPECL output pairs
Two differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
Output skew: 8ps (typical)
Propagation delay: 270ps (maximum)
Low additive phase jitter, RMS: 47fs (maximum)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (IEE): 93mA (maximum)
Available in lead-free (RoHS 6), 28-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
Pin Assignment
21 20 19 18 17 16 15
QB0 22
14 VEE
nQB0 23
13 nQA0
QB1 24
12 QA0
nQB1 25
11 VREFA
QB2 26
10 nPCLKA
nQB2 27
9 PCLKA
VCC 28
8 VCC
1 23 45 67
8SLVP2104I
28-Lead VFQFN
5mm x 5mm x 0.75mm package body
NB Package
Top View
8SLVP2104 REVISION C 6/8/15
1 ©2015 Integrated Device Technology, Inc.







8SLVP2104 pdf, 数据表
8SLVP2104 DATA SHEET
Parameter Measurement Information
2V
SCOPE
VCC Qx
nQx
VEE
-1.3V± 0.165V
3.3V LVPECL Output Load AC Test Circuit
2V
SCOPE
VCC
Qx
nQx
VEE
-0.5V±0.125V
2.5V LVPECL Output Load AC Test Circuit
VCC
nPCLKA,
nPCLKB
PCLKA,
PCLKB
VEE
V
PP
Cross Points
Differential Input Level
V
CMR
Part 1
nQx
Qx
Part 2
nQy
Qy
t sk(pp)
Part-to-Part Skew
nQx
Qx
nQy
Qy
Output Skew
nPCLKA, nPCLKB
PCLKA, PCLKB
nQy
Qy
t PLH
tsk(p)= |tPHL - tPLH|
Pulse Skew
t PHL
LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8
REVISION C 6/8/15







8SLVP2104 equivalent, schematic
8SLVP2104 DATA SHEET
Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 6B can be eliminated and the termination is
shown in Figure 6C.
VCC = 2.5V
50Ω
50Ω
2.5V LVPECL Driver
2.5V
R1
250Ω
R3
250Ω
2.5V
+
R2
62.5Ω
R4
62.5Ω
VCC = 2.5V
50Ω
50Ω
2.5V LVPECL Driver
2.5V
+
R1 R2
50Ω 50Ω
R3
18Ω
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
VCC = 2.5V
50Ω
50Ω
2.5V LVPECL Driver
2.5V
+
R1 R2
50Ω 50Ω
Figure 6C. 2.5V LVPECL Driver Termination Example
LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
16
REVISION C 6/8/15










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