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PDF ( 数据手册 , 数据表 ) 8P34S2104

零件编号 8P34S2104
描述 Dual 1:4 LVDS Output 1.8V Fanout Buffer
制造商 IDT
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8P34S2104 数据手册, 描述, 功能
Dual 1:4 LVDS Output 1.8V Fanout Buffer
8P34S2104
Datasheet
Description
The 8P34S2104 is a high-performance, low-power, differential
dual 1:4 LVDS Output 1.8V fanout buffer. The device is designed
for the fanout of high-frequency, very low additive phase-noise
clock and data signals. Two independent buffer channels are
available. Each channel has four low-skew outputs. High isolation
between channels minimizes noise coupling. AC characteristics
such as propagation delay are matched between channels.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8P34S2104 ideal for those clock distribution
applications demanding well-defined performance and
repeatability. The device is characterized to operate from a 1.8V
power supply. The integrated bias voltage references enable easy
interfacing of AC-coupled signals to the device inputs.
Block Diagram
Features
Dual 1:4 low skew, low additive jitter LVDS fanout buffers
Matched AC characteristics across both channels
High isolation between channels
Low power consumption
Both differential CLKA, nCLKA and CLKB, nCLKB inputs
accept LVDS, LVPECL and single-ended LVCMOS levels
Maximum input clock frequency: 2GHz
Output amplitudes: 350mV, 500mV (selectable)
Output bank skew: 8ps typical
Output skew: 10ps typical
Low additive phase jitter, RMS: 45fs typical
(fREF = 156.25MHz, 12kHz - 20MHz)
Full 1.8V supply voltage mode
Device current consumption (IDD): 135mA typical
Lead-free (RoHS 6), 28-lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature up to 105°C
CLKA
nCLKA
VDDQA
51k
51k 51k
VREFA
Voltage
Reference A
VDDQB
CLKB
nCLKB
51k
51k 51k
VDDQB
VREFB
SELA
Voltage
Reference B
8P34S2104 transistor count:
51k
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
©2016 Integrated Device Technology, Inc.
1
October 20, 2016







8P34S2104 pdf, 数据表
8P34S2104 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value
of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.
When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Figure 2. Additive Phase Jitter. Frequency: 156.25MHz, Integration range: 12kHz to 20MHz = 45fs typical
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
©2016 Integrated Device Technology, Inc.
8
October 20, 2016







8P34S2104 equivalent, schematic
Package Drawings
Figure 10. 28-lead VFQFN Package Outline and Dimensions
8P34S2104 Datasheet
©2016 Integrated Device Technology, Inc.
16
October 20, 2016










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