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PDF ( 数据手册 , 数据表 ) DAC8841

零件编号 DAC8841
描述 CMOS TrimDAC
制造商 Analog Devices
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DAC8841 数据手册, 描述, 功能
ANALOG
DEVICES
8-Bit Octal, 2-Quadrant
Multiplying, CMOS TrimDAC
FEATURES
Replaces 8 Potentiometers
Operates From Single +5 V Supply
1 MHz 2-Quadrant Muitipiying Bandwidth
No Signal Inversion
Eight Individual Channels
3-Wire Serial Input
500 kHz Update Data Loading Rate
+3 Volt Output Swing
Midscale Preset
Low 95 mW Power Dissipation
APPLICATIONS
Trimmer Replacement
Dynamic Level Adjustment
Special Waveform Generation and Modulation
Programmable Gain Amplifiers
GENERAL DESCRIPTION
The DAC-8841 provides eight general purpose digitally controDed
voltage adjustment devices. The TrimDAC™ capability replaces
the mechanical trimmer function in new designs. It is ideal for
ac or dc gain control of up to 1 MHz bandwidth signals.
Internally the DAC-8841 contains eight voltage output CMOS
digital-to-analog converters, each wi± separate reference inputs.
Each DAC has its own DAC register which holds its output
state. These DAC registers are updated from an internal serial-
to-parallel shift register which is loaded from a standard 3-wire
serial input digital interface. Twelve data bits make up the data
word clocked into the serial input register. This data word is
decoded where the first 4 bits determine the address of the DAC
register to be loaded with the last 8 bits of data. A serial data
output pin at the opposite end of the serial register allows sim
ple daisy-chaining in multiple DAC applications without addi
tional external decoding logic.
TrimDAC is a trademark of Analog Devices, Inc.
DAC-8841 FUNCTIONAL BLOCK DIAGRAM
LOAD i
QND SDO PRESET V^gpL
The DAC-8841 consumes only 95 mW froir a -1-5 V power sup
ply. For dual polarity applications see the DAC-8840 which pro
vides full 4-quadrant-multiplying ±3 V signal capability while
operating from ±5 V power supplies.
The DAC-8841 is available in 24-pin plastic DIP, cerdip, and
SOIC-24 packages. For MIL-STD/883 applications, contact
ADI sales for the DAC-8841BW/883 data sheet which specifies
operation over -55®C to 4-125°C.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use; nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
Twx: 710/394-6577
Telex: 924491
Cable: ANALOG NORWOODMASS







DAC8841 pdf, 数据表
DAC-8841
CIRCUIT OPERATION
The DAC-8841 is a general purpose multiple-channel ac or do
signal level adjustment device designed to replace potentiometers
used in the three-terminal connection mode. Eight independent
channels of programmable signal level control are available in
this 24-pin package device. The outputs are completely buffered
providing up to 5 mA of drive current to drive external loads.
The DAG and amplifier combination shown in Figure 18 pro
duces two-quadrant multiplication of the signal inputs applied to
ViN times the digital input control word. In addition the DAC-
8841 provides a 1 MHz gain-bandwidth product in the two-
quadnmt multiplying channel. Operating from a 5 V power
supply, analog inputs to +1.5 V which generate outputs to
+3 V are easily accommodated.
During system power up a logic low on the preset PR pin forces
all DAC registers to 80^ which in turn forces all the buffer am
plifier outputs to equal half-scale. The transfer equation (1)
shows that in the preset condition (80h) that Vqut will equal
ViN. The asynchronous PR input pin can be activated at any
time to force the DAC registers to the half-scale code 80h. This
is generally the most convenient place to start for general pur
pose adjustment applications.
ADJUSTING AC OR DC SIGNAL LEVELS
The two-quadrant multiplication operation of the DAC-8841 is
shown in Figiure 18. For dc operation the equation describing
the relationship between Vjn, digital inputs and Vqut is:
VouiiD) = (D/128) X (V/jv - VrefL) + Vref^ (1)
where D is a decimal number between 0 and 255.
The acmal output voltages generated with a fixed 1.5 V dc input
on VjN and VrefL = 0 V are summarized in this table.
Vqut = 2 XVdac when Vrepl =ov
:r2(D/256)xV,M
= (D/128)xV,n
GENERALCASE WHENVrep L x OV:
VouT= (D/128)x (V|n- Vref L) + Vrhf L
DAC8841 INPUT-OUTPUT VOLTAGE RANGE
VpD = tSV
Vref' .=ov
n - FF..
71
/ .DsCOh
(I~—X
O
CO
^ aD=40h
1
DsOOh
02 4
V,N-Volts
Vqut= 2 XV,n (D/256). where D=0 TO255
Figure 18. DAC Plus Amplifier Combine to Produce Two-
Quadrant Multiplication
In order to be easy to use with a controlling microprocessor, a
simplelayout-efficient three-wire serial data interface was cho
sen. This interface can be easily adapted to almost all microcom
puter and microprocessor systems. A clock (CLK), serial data
input (SDI) and a load(LD) strobe pin make up the three-wire
interface. The 12-bitinput data word used to change the value
of the internal DAC registerscontains a 4-bit address and 8-bits
of data. Using this combination, any DAC registercan be
changed without disturbing the other devices. A serialdata out
put (SDO) pin simplifies cascading multiple DAC-8841s without
adding address decoder chips to the system.
Decimal Input (D)
0
1
2
127
128
129
254
255
Vout(®)
0.000 V*
0.012*
0.024*
1.488
1.500
1.512
2.976
2.988
Comments
(ViN = 1.5 V, VrefL = 0 V)
Zero Scale
Half Scale = Vin
Full Scale
(FS) « 2 X ViN
*See "Operation Near Ground."
Notice that the output polarity is the same as the input polarity
when the DAC register is loaded with 255 (in binary = all
ones). Also note that the output does not exactly equal two
times the input voltage. This is a result of the R-2R ladder DAC
chosen. When the DAC register is loaded with 0, the output is
VrefL. The acmal voltage measured when setting up a DAC in
this example will vary within the ± 1 LSB linearity error specifi
cation of the DAC-8841. The actual voltage error would be
±0.012 V.
Operation Near ground - The input stage of the internal buffer
amplifier functions down to groimd, but the output stage cannot
pull lower than the internal ground voltage. When a DAC out
put tries to output a voltage at or below the internal ground po
tential, it saturates and appears like a 50 fl resistor to ground.
The typical saturation voltage appearing at the output is 20 mV,
see Figure 9. The 100 mV worst case zero-scale voltage specifi
cation reflects this saturation effect, including the worst case
anticipated variationof the internal ground resistances, quies
cent currents and buffer sinking current. Linearity is measured
betweencode 8io and code 255^0 to avoid this samration effect.
In summary, the transfer function of each DAC will be a
straight line from code 8 to code 255 when VrefL = 0 V. For
input codes 0 to 7, some DAC outputs will be satiurated in the
zero-scale output voltage region; therefore, changing digjtal code
0 to 1 may not change the output voltage when VrefL - 0 V.
-8-














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