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PDF ( 数据手册 , 数据表 ) 2EDN8523F

零件编号 2EDN8523F
描述 EiceDRIVER MOSFET
制造商 Infineon
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2EDN8523F 数据手册, 描述, 功能
EiceDRIVER™
2EDN752x / 2EDN852x
Fast, precise, strong and compatible
• Highly efficient SMPS enabled by 5 ns fast slew rates and 17 ns propagation delay precision for fast MOSFET
and GaN switching
• 1 ns channel-to-channel propagation delay accuracy enables safe use of two channels in parallel
• Two independent 5 A channels enable numerous deployment options
• Industry standard packages and pinout ease system-design upgrades
The new Reference in Ruggedness
• 4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET protection under abnormal
conditions
• -10 V control and enable input robustness delivers crucial safety margin when driving pulse-transformers or
driving MOSFETs in through hole packaging
• 5 A reverse current robustness eliminates the need for output protection circuitry.
Typical Applications
• Server SMPS
• TeleCom SMPS
• DC-to-DC Converter
• Bricks
• Power Tools
• Industrial SMPS
• Motor Control
• Solar SMPS
Example Topologies
• Single and interleaved PFC
• LLC, ZVS with pulse transformer
• Synchronous Rectification
Description
The 2EDN752x/2EDN852x is an advanced dual-channel driver. It is suited to drive logic and normal level MOSFETs
and supports OptiMOSTM, CoolMOSTM, Standard Level MOSFETs, Superjunction MOSFETs, as well as IGBTs and
GaN Power devices.
The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to +20 V.
-10 V input pin robustness protects the driver against latch-up or electrical overstress which can be induced by
parasitic ground inductances. This greatly enhances system stability.
Data Sheet
Please read the Important Notice and Warnings at the end of this document
www.infineon.com
Revision 2.3
2016-10-05







2EDN8523F pdf, 数据表
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
The pin configuration for direct input versions of 2EDN7524G and 2EDN7523G in the PG-WSON-8-1 package is
shown in Figure 3. Drawings can be viewed in Chapter 8 (PG-WSON-8-1).
ENA 1
8 ENB
INA 2
GND 3
Exposed
Pad
7 OUTA
6 VDD
INB 4
5 OUTB
Figure 3 Pin Configuration PG-WSON-8-1, Top View
Table 5 Pin Configuration 2EDN7524G and 2EDN7523G in the PG-WSON-8-1 Package
Pin Symbol Description
1 ENA
Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2 INA
Input signal channel A
Logic input, controlling OUTA (non-inverting)
3 GND
Ground1)
4 INB
Input signal channel B
Logic input, controlling OUTB (non-inverting)
5 OUTB Driver output channel B
Low-impedance output with source and sink capability
6 VDD
Positive supply voltage
Operating range 4.5 V/8.6V to 20 V
7 OUTA
Driver output channel A
Low-impedance output with source and sink capability
8 ENB
Enable input channel B
Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low
1)Exposed Pad of PG-WSON-8-1 packages has to be connected to GND pin.
Data Sheet
8
Revision 2.3
2016-10-05







2EDN8523F equivalent, schematic
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 13 Static Output Caracteristics (see Figure 7)
Parameter
Symbol
Values
Unit Note or Test Condition
Min. Typ. Max.
High Level (Sourcing) Output RONSRC 0.35
0.7
1.2
ISRC = 50mA
Resistance
High Level (Sourcing) Output ISRCPEAK
Current
5.0 1)
A
Low Level (Sinking) Output RONSNK 0.28 0.55 1.0
Resistance
ISNK = 50mA
Low Level (Sinking) Output
Current
ISNKPEAK
-5.0 2)
A
1) Active limited by design at approx. 6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
2) Active limited by design at approx. -6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
Table 14 Dynamic Characteristics (see Figure 6, Figure 7, Figure 8 and Figure 9)
Parameter
Symbol
Values
Unit Note or Test Condition
Min. Typ. Max.
Input/Enable to output
TPDlh
15
17
23
ns CLOAD= 1.8 nF, VVDD= 12 V;
propagation delay
low to high transition at
Input/Enable
Input/Enable to output
TPDhl
15
19
23
ns CLOAD= 1.8 nF, VVDD= 12 V
propagation delay
high to low transition at
Input/Enable
Input/Enable to output
delta tPD
propagation delay mismatch
between the two channels on
the same IC
2 ns
Rise Time
Fall Time
Minimum input pulse width
that changes output state
TRISE
TFAll
TPW
5.3 10 1) ns CLOAD= 1.8 nF, VVDD= 12 V
4.5 10 1) ns CLOAD= 1.8 nF, VVDD= 12 V
6 10 1) ns CLOAD= 1.8 nF, VVDD= 12 V
1) Parameter verified by design, not 100% tested in production.
Data Sheet
16
Revision 2.3
2016-10-05










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