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PDF ( 数据手册 , 数据表 ) 1EDI30J12CP

零件编号 1EDI30J12CP
描述 Single JFET Driver IC
制造商 Infineon
LOGO Infineon LOGO 


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1EDI30J12CP 数据手册, 描述, 功能
1EDI EiceDRIVER™ Enhanced
1EDI30J12CP
Single JFET Driver IC
Preliminary Datasheet
Rev. 1.3, November 2014
Industrial Power Control







1EDI30J12CP pdf, 数据表
3 Functional Description
EiceDRIVER™ Enhanced
1EDI30J12CP
Functional Description
3.1 Introduction
The 1EDI30J12Cx is an advanced JFET (junction gate field-effect transistor) gate driver. The driver is built to drive
a normally-on CoolSiCTM JFET together with a low voltage p-channel MOSFET in a switching loss optimized
cascode operation called Direct Drive JFET Topology.
As MOSFET (metal–oxide–semiconductor field-effect transistor; referred to as pMOS, LV MOSFET) a 30 V p-
channel OptiMOSTM MOSFET with low RDSon is typically used (e.g. OptiMOSTM BSC030P03NS3 G).
The driver consists of two galvanic separated parts. The inputs can be connected to any controller with varying
signal levels. The pins can handle signals up to 17.5V, however the thresholds remains at TTL levels.
The output side is connected to the high voltage side of the application, incorporates two rail to rail output stages.
The two gate drivers, one for the JFET and one for the MOSFET, drive the gates between VCC2 and the regulated
output VREG.
The 1EDI30J12Cx supports two different start up modes selectable by the bootstrap enable pin BSEN. A
specialized bootstrap operation mode for supplying the driver via a bootstrap diode. And a standard operation
mode for direct supply realised with a floating isolated supply source.
The output side has a built in linear voltage regulator to generate an accurate JFET driver supply voltage inside
the window between pinch off voltage and punch through voltage of Infineon’s CoolSiCTM JFETs . In addition, the
internal regulator separates the driver supply voltage from a common supply voltage for low side switches, so all
low side switches could be supplied by one negative supply. Further in isolated supply topologies it offers the
support of wide supply range due to preregulation. So voltage drops due to bad transformer coupling can be
handled.
Cascodes were introduced in the past for faster switching made possible by the elimination of the JFETs Cgd
acting as a feedback to the control gate. The disadvantage by eliminating the feedback is that the dV/dt of the
switch gets uncontrolled.
New JFET devices like CoolSiCTM JFET offers a reduced gate charge, therefore driving the JFET gate directly
offers advantages in controlling the switching speed with lower EMI and less ringing.
3.2 Theory of Operation
The optimized cascode operation offered by the 1EDI30J12Cx driver called Direct Drive JFET Topology differs
from the normal cascode in the way it is controlling the switch. The normal cascode controls the normally-on JFET
by indirectly controlling the source potential of the JFET via the low-voltage MOSFET.
In the Direct Drive JFET Topology the MOSFET is used to keep the normally-on JFET in a safe off-state during
start up of the application as in the normal cascode. When the driver auxilliary supply voltage is high enough to
release the Under Voltage Lock Out (UVLO) the MOSFET is permanently turned on and the JFET is driven directly
according to the input signal.
The input signal is transferred across the isolating Coreless Transformer (CLT) from input side to output side. A
high at the input pin turns on the JFET. The 1EDI30J12Cx is a non inverting driver.
When the VCC1 supply voltage has reached the turn on threshold and the signal at the EN pin is high, the input
side is able to send the IN signal to the output side.
Depending on the UVLO of the output side, the input signal is either ignored if |VVREG| is below the UVLO-on-
threshold or is applied amplified at the gate of JFET.
When the VCC1 voltage potential reaches the turn off threshold, the input side sends an off signal to the output
side to ensure a defined switch off state before the driver is disabled.
The driver can be disabled using the EN pin: in case the EN pin is pulled to low, the output is switched off
regardless of the signal applied to the IN pin.
Preliminary Datasheet
7
Rev. 1.3, 2014-11-12







1EDI30J12CP equivalent, schematic
4.2 Thermal Characteristics
EiceDRIVER™ Enhanced
1EDI30J12CP
Characteristics
Table 3 Thermal Characteristics
Parameter
Thermal resistance Junction-Ambient
Symbol
RthJA25
Values
Typ.
85
Unit Remarks
K/W PG-DSO-19-4, TA=25°C;
Layout: Figure 16
4.3 Operating Range
Table 4 Operating Range
Parameter
Symbol Limit Values
Unit Remarks
Min.
Max.
Positive supply voltage input side
VVCC1
Logic input voltage input side (IN, EN) VIN
Negative supply voltage output side VVEE2
(VEE2)
4.75
0
-28
17.5
VVCC1
-22
V
V
V
VREG in regulation, full
PSRR
Negative supply voltage output side VVEE2
(VEE2)
-28
-19 V VVREG > VVREGoff1)
Output capacitance for VREG
CVREG
0.22
2.2 µF
Common mode transient immunity |dVISO/dt|
100 V/ns
Junction temperature
TJ -40 150 °C
1) The parameter is not subject to production test - verified by design/characterization
2) According to product qualification conditions (tested according to EIA/JESD22-A108D)
from VREG to VCC21),
ESRCVREG < 15mOhm
1)
1)2)
Preliminary Datasheet
15
Rev. 1.3, 2014-11-12










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