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PDF ( 数据手册 , 数据表 ) MC74HC4060

零件编号 MC74HC4060
描述 14-Stage Binary Ripple Counter
制造商 Motorola Semiconductors
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MC74HC4060 数据手册, 描述, 功能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter with Oscillator
High–Performance Silicon–Gate CMOS
The MC54/74HC4060 is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator with a
frequency that is controlled either by a crystal or by an RC circuit connected
externally. The output of each flip–flop feeds the next, and the frequency at
each output is half that of the preceding one. The state of the counter
advances on the negative–going edge of Osc In. The active–high Reset is
asynchronous and disables the oscillator to allow very low power consump-
tion during standby operation.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may need to be gated with Osc Out 2 of the HC4060.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
LOGIC DIAGRAM
OSC OUT 1 OSC OUT 2
10 9
OSC IN 11
7 Q4
5 Q5
4 Q6
6 Q7
14 Q8
13 Q9
15 Q10
1 Q12
2 Q13
3 Q14
RESET 12
PIN 16 = VCC
PIN 8 = GND
MC54/74HC4060
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDT
Ceramic
Plastic
TSSOP
PIN ASSIGNMENT
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
GND 8
16 VCC
15 Q10
14 Q8
13 Q9
12 RESET
11 OSC IN
10 OSC OUT 1
9 OSC OUT 2
Clock
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Change
Advance to Next State
All Outputs are Low
10/95
© Motorola, Inc. 1995
1 REV 6







MC74HC4060 pdf, 数据表
MC54/74HC4060
OSC IN
RESET
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
TIMING DIAGRAM
12
4
8
16 32
64
128 256
512 1024 2048 4096 8192 16,384
MOTOROLA
8 High–Speed CMOS Logic Data
DL129 — Rev 6














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