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PDF ( 数据手册 , 数据表 ) NB3N206S

零件编号 NB3N206S
描述 3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver
制造商 ON Semiconductor
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NB3N206S 数据手册, 描述, 功能
NB3N201S, NB3N206S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N20xS Series are pure 3.3 V supply differential Multipoint
Low Voltage (M−LVDS) line Drivers and Receivers. Devices
NB3N201S and NB3N206S are TIA/EIA−899 compliant. NB3N201S
offers the Type 1 receiver threshold at 0.0 V. NB3N206S offers the
Type 2 receiver threshold at 0.1 V.
These devices have Type−1 and Type−2 receivers that detect the bus
state with as little as 50 mV of differential input voltage over a
common−mode voltage range of −1 V to 3.4 V. The Type−1 receivers
have near zero thresholds (±50 mV) and exhibit 25 mV of differential
input voltage hysteresis to prevent output oscillations with slowly
changing signals or loss of input. Type−2 receivers include an offset
threshold to provide a detectable voltage under open−circuit, idle−bus,
and other faults conditions.
NB3N201S and NB3N206S support Simplex or Half Duplex bus
configurations.
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
NB20x
AYWW
G
1
NB20x
x
A
Y
WW
G or G
= Specific Device Code
= 1, 6
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
Features
Low−Voltage Differential 30 W to 55 W Line Drivers
and Receivers for Signaling Rates Up to 200 Mbps
Type−1 Receivers Incorporate 25 mV of Hysteresis
Type−2 Receivers Provide an Offset (100 mV)
Threshold to Detect Open−Circuit and Idle−Bus
Conditions
Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3 ±10% V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
These are Pb−Free Devices
Applications
Low−Power High−Speed Short−Reach Alternative to
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1
Publication Order Number:
NB3N201S/D







NB3N206S pdf, 数据表
NB3N201S, NB3N206S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf1 ns, pulse frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20% tolerance.
C. R1 and R2 are metal film, surface mount, 1% tolerance, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Test Circuit and Definitions for the Driver Common−Mode Output Voltage
Figure 6. Driver Short−Circuit Test Circuit
A. All input pulses are supplied by a generator having the following characteristics: tr or tf1 ns, frequency = 500 kHz,
duty cycle = 50 ±5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 7. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
www.onsemi.com
8







NB3N206S equivalent, schematic
NB3N201S, NB3N206S
Figure 17. M−LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
Simplex Theory Configurations: Data flow is
unidirectional and Point−to−Point from one Driver to one
Receiver. NB3N201SDG and NB3N206SDG devices
provide a high signal current allowing long drive runs and
high noise immunity. Single terminated interconnects yield
high amplitude levels. Parallel terminated interconnects
yield typical MLVDS amplitude levels and minimizes
reflections. See Figures 18 and 19. A NB3N201SDG and
NB3N206SDG can be used as the driver or as a receiver.
Figure 18. Point−to−Point Simplex Single
Termination
Simplex Multidrop Theory Configurations: Data flow is
unidirectional from one Driver with one or more Receivers
Multiple boards required. Single terminated interconnects
yield high amplitude levels. Parallel terminated
interconnects yield typical MLVDS amplitude levels and
Figure 19. Parallel−Terminated Simplex
minimizes reflections. On the Evaluation Test Board,
Headers P1, P2, and P3 may be used as need to interconnect
transceivers to a each other or a bus. See Figures 20 and 21.
A NB3N201SDG and NB3N206SDG can be used as the
driver or as a receiver.
www.onsemi.com
16










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