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PDF ( 数据手册 , 数据表 ) NB3N200S

零件编号 NB3N200S
描述 3.3 V Differential Multipoint Low Voltage M-LVDS Driver Receiver
制造商 ON Semiconductor
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NB3N200S 数据手册, 描述, 功能
NB3N200S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N200 is a pure 3.3 V supply differential Multipoint Low
Voltage (M−LVDS) line Driver and Receiver. NB3N200S is
TIA/EIA−899 compliant. NB3N200S offers the Type 1 receiver
threshold at 0.0 V.
These devices has a Type−1 receiver that detect the bus state with as
little as 50 mV of differential input voltage over a common−mode
voltage range of −1 V to 3.4 V. The Type−1 receivers have near zero
thresholds (±50 mV) and exhibit 25 mV of differential input voltage
hysteresis to prevent output oscillations with slowly changing signals
or loss of input.
NB3N200S supports Simplex or Half Duplex bus configurations.
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
NB20x
AYWW
G
1
NB20x
x
A
Y
WW
G or G
= Specific Device Code
= 0, 2, 4, 5
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Features
Low−Voltage Differential 30 W to 55 W Line Drivers and Receivers
for Signaling Rates Up to 200 Mbps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Type−1 Receivers Incorporate 25 mV of Hysteresis
Meets or Exceeds the M−LVDS Standard TIA/EIA−899 Pb−Free SOIC 8 Package
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3 ±10% V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
These are Pb−Free Devices
Applications
Low−Power High−Speed Short−Reach Alternative to
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
Figure 1. Logic Diagrams
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1
Publication Order Number:
NB3N200S/D







NB3N200S pdf, 数据表
NB3N200S
A. All input pulses are supplied by a generator having the following characteristics: tr or tf1 ns, frequency = 500 kHz,
duty cycle = 50 ±5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are 20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 8. Driver Enable and Disable Time Circuit and Definitions
Figure 9. Maximum Steady State Output Voltage
www.onsemi.com
8







NB3N200S equivalent, schematic
NB3N200S
Figure 20. Multidrop or Distributed Simplex with Single Termination
Figure 21. Multidrop or Distributed Simplex with Double Termination
Half Duplex Multinode Multipoint Theory
Configurations: Data flow is unidirectional and selected
from one of multiple possible Drivers to multiple Receives.
One “Two Node” multipoint connection can be
accomplished with a single evaluation board. More than
Two Nodes requires multiple evaluation test boards. Parallel
terminated interconnects yield typical MLVDS amplitude
levels and minimizes reflections. Parallel terminated
interconnects yield typical LMVDS amplitude levels and
minimizes reflections. On the Test Board, Headers P1, P2,
and P3 may be used as need to interconnect transceivers to
each other or a bus. See Figure 22. A NB3N202SDG,
NB3N204SDG, and NB3N205SDG can be used as the
driver or as a receiver. Full duplex bus interconnect
configurations are possibe using NB3N202SDG or
NB3N205SDG.
Figure 22. Multinode Multipoint Half Duplex (requires Double Termination)
Figure 23.
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