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PDF ( 数据手册 , 数据表 ) ADRF6720-27

零件编号 ADRF6720-27
描述 Wideband Quadrature Modulator
制造商 Analog Devices
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ADRF6720-27 数据手册, 描述, 功能
Data Sheet
Wideband Quadrature Modulator with
Integrated Fractional-N PLL and VCOs
ADRF6720-27
FEATURES
I/Q modulator with integrated fractional-N PLL
RF output frequency range: 400 MHz to 3000 MHz
Internal LO frequency range: 356.25 MHz to 2855 MHz
Output P1dB: 10.8 dBm at 2140 MHz
Output IP3: 31.1 dBm at 2140 MHz
Carrier feedthrough: −44.3 dBm at 2140 MHz
Sideband suppression: −40.8 dBc at 2140 MHz
Noise floor: −159.5 dBm/Hz at 2140 MHz
Baseband 1 dB modulation bandwidth: >1000 MHz
Baseband input bias level: 2.68 V
Power supply: 3.3 V/425 mA
Integrated RF tunable balun allowing single-ended RF output
Multicore integrated VCOs
HD3/IP3 optimization
Sideband suppression and carrier feedthrough optimization
High-side/low-side LO injection
Programmable via 3-wire serial port interface (SPI)
40-lead 6 mm × 6 mm LFCSP
APPLICATIONS
2G/3G/4G/LTE broadband communication systems
Microwave point-to-point radios
Satellite modems
Military/aerospace
Instrumentation
GENERAL DESCRIPTION
The ADRF6720-27 is a wideband quadrature modulator with an
integrated synthesizer ideally suited for 3G and 4G com-
munication systems. The ADRF6720-27 consists of a high
linearity broadband modulator, an integrated fractional-N
phase-locked loop (PLL), and four low phase noise multicore
voltage controlled oscillators (VCOs).
The ADRF6720-27 local oscillator (LO) signal can be generated
internally via the on-chip integer-N and fractional-N synthesizers,
or externally via a high frequency, low phase noise LO signal.
The internal integrated synthesizer enables LO coverage from
356.25 MHz to 2855 MHz using the multicore VCOs. In the
case of internal LO generation or external LO input, quadrature
signals are generated with a divide by 2 phase splitter. When the
ADRF6720-27 is operated with an external 1 × LO input, a
polyphase filter generates the quadrature inputs to the mixer.
The ADRF6720-27 offers digital programmability for carrier
feedthrough optimization, sideband suppression, HD3/IP3
optimization, and high-side or low-side LO injection.
The ADRF6720-27 is fabricated using an advanced silicon-
germanium BiCMOS process. It is available in a 40-lead,
RoHS-compliant, 6 mm × 6 mm LFCSP package with an
exposed pad. Performance is specified over the −40°C to +85°C
temperature range.
FUNCTIONAL BLOCK DIAGRAM
VPOSx
I+ 3
I– 4
40 35 30
V TO I
LO NULLING
DAC
26
22 17 11
PHASE
CORRECTION
6
ADRF6720-27
27 ENBL
24 RFOUT
Q– 8
Q+ 9
REFIN 39
CP 36
VTUNE 32
LO NULLING
DAC
V TO I
PLL
QUAD
DIVIDER
LOIN– 33
LOIN+ 34
POLYPHASE
FILTER
2 5 7 10 16 20 23 25 29 37 38
GND
PHASE
CORRECTION
18 LOOUT+
19 LOOUT–
LDO
2.5V
LDO
VCO
12 28
DECL1 DECL2
SERIAL
PORT
INTERFACE
31
DECL3
15 CS
14 SCLK
13 SDIO
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADRF6720-27 pdf, 数据表
Data Sheet
ADRF6720-27
Parameter
BASEBAND INPUTS
I and Q Input DC Bias Level
Bandwidth
Differential Input
Impedance
Differential Input
Capacitance
OUT ENABLE
Turn-On Settling Time
Turn-Off Settling Time
DIGITAL LOGIC
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current (IIH/IIL)
Input Capacitance (CIN)
Output Voltage High (VOH)
Output Voltage Low (VOL)
POWER SUPPLIES
Voltage Range
Supply Current
Test Conditions/Comments
I± and Q± pins
Min
1 dB
Frequency = 100 MHz2
Frequency = 100 MHz2
ENBL pin
ENBL low to high (90% of envelope), when Register 0x01[10] =
1, Register 0x10[10] = 1
ENBL high to low (10% of envelope), when Register 0x01[10] =
1, Register 0x10[10] = 1
SCLK, SDIO, CS, and ENBL
1.4
−1
IOH = −100 µA
IOL = +100 µA
2.3
VPOSx
Tx mode at internal LO mode (PLL, internal VCO , and modulator
enabled, LO output driver disabled)
Tx mode at external 1× LO mode (PLL, internal VCO disabled,
modulator enabled, LO output driver disabled)
LO output driver; LO_DRV_LVL bits (Register 0x22[7:6]) = 10
Power-down mode
Typ Max Unit
2.68
>1000
55
0.97
V
MHz
pF
170 ns
10 ns
V
0.7 V
+1 µA
5 pF
V
0.2 V
3.3 V
425 mA
218 mA
42 mA
14.5 mA
1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) − 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF =
153.6 MHz, fREF power = 4 dBm with a 38.4 MHz fPFD. The FOM was computed at a 50 kHz offset.
2 Refer to Figure 47 for a plot of input impedance over frequency.
TIMING CHARACTERISTICS
Table 2.
Parameter
tSCLK
tDS
tDH
tS
tH
tHIGH
tLOW
tACCESS
tz
Description
Serial clock period
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Setup time between falling edge of CS and SCLK
Hold time between rising edge of CS and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Maximum time delay between falling edge of SCLK and output data valid for a read operation
Maximum time delay between CS deactivation and SDIO bus return to high impedance
Min Typ Max Unit
38 ns
8 ns
8 ns
10 ns
10 ns
10 ns
10 ns
13 ns
5 ns
tDS tHIGH
tS tDH
CS
SCLK DON'T CARE
tSCLK
tLOW
tACCESS
SDIO DON'T CARE
A6 A5 A4 A3 A2 A1 A0 R/W D15 D14 D13
Figure 2. Serial Port Timing Diagram
Rev. B | Page 7 of 43
tH
D3 D2 D1 D0
DON'T CARE
tZ
DON'T CARE







ADRF6720-27 equivalent, schematic
Data Sheet
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
TA = –40°C
TA = +25°C
TA = +85°C
900
1400
1900
2400
LO FREQUENCY (MHz)
Figure 28. Integrated Phase Noise with Spurs vs. LO Frequency and
Temperature
–40
–60
–80
–100
–120
–140
2858.07MHz
2578.49MHz
2302.24MHz
–160
1k
10k 100k
1M
10M
100M
FREQUENCY (Hz)
Figure 29. Open-Loop VCO Phase Noise for VCO 0 Measured at 2302.24 MHz,
2578.49 MHz, and 2858.07 MHz (VCO ÷ 2)
–40
–60
–80
–100
–120
–140
2011.44MHz
1880.53MHz
1750.79MHz
–160
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 30. Open-Loop VCO Phase Noise for VCO 2 Measured at 1750.79 MHz,
1880.53 MHz, and 2011.44 MHz (VCO ÷ 2)
ADRF6720-27
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
2800
3300
3800
4300
4800
5300
5800
VCO FREQUENCY (MHz)
Figure 31. VTUNE vs. VCO Frequency and Temperature
–40
–60
–80
–100
–120
–140
2303.74MHz
2156.68MHz
2009.39MHz
–160
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 32. Open-Loop VCO Phase Noise for VCO 1 Measured at 2009.39 MHz,
2156.68 MHz, and 2303.74 MHz (VCO ÷ 2)
–40
–60
–80
–100
–120
–140
1750.85MHz
1588.9MHz
1425.84MHz
–160
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 33. Open-Loop VCO Phase Noise for VCO 3 Measured at 1425.84 MHz,
1588.9 MHz, and 1750.85 MHz (VCO ÷ 2)
Rev. B | Page 15 of 43










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