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PDF ( 数据手册 , 数据表 ) NB3L202K

零件编号 NB3L202K
描述 Differential 1:2 HCSL Fanout Buffer
制造商 ON Semiconductor
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NB3L202K 数据手册, 描述, 功能
NB3L202K
2.5 V, 3.3 V Differential 1:2
HCSL Fanout Buffer
Description
The NB3L202K is a differential 1:2 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
Features
Maximum Input Clock Frequency > 350 MHz
2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
2 HCSL Outputs
DB200H Compliant
Individual OE Control Pin for Each Output
100 ps Max Output−to−Output Skew Performance
1 ns Typical Propagation Delay
500 ps Typical Rise and Fall Times
80 fs Maximum Additive RMS Phase Jitter
−40°C to +85°C Ambient Operating Temperature
QFN 16−pin Package, 3 mm x 3 mm
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
PCI Express
FBDIMM
Mobile Computing
Networking
Gigabit Ethernet
www.onsemi.com
MARKING
DIAGRAM
QFN16
1
NB3L
3x3 202K
1
CASE 485AE
ALYWG
G
NB3L202K = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information page 13 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 0
1
Publication Order Number:
NB3L202K/D







NB3L202K pdf, 数据表
NB3L202K
Table 6. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS
(VDD = VDD_O = 3.3 V ±10% or 2.5 V ±5%, TA = −40°C to 85°C)
Symbol
Parameter
Conditions (Notes 34 and 39)
Min Typ Max Unit
tjphPCIeG1
tjphPCIeG2
PCIe Gen 1 (Notes 35 and 36)
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Notes 35 and 38)
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Notes 35 and 38)
10 ps (p−p)
0.3
ps
(rms)
0.7
ps
(rms)
tjphPCIeG3 Additive Phase Jitter
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Notes 35 and 38)
0.3
ps
(rms)
QPI & SMI
(100.00 MHz or 133.33 MHz, 4.8 Gb/s,
6.4 Gb/s 12UI) (Notes 37 and 38)
0.3
ps
(rms)
tjphQPI_SMI
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Notes 37 and 38)
0.1
ps
(rms)
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Notes 37 and 38)
0.1
ps
(rms)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
34. Applies to all outputs.
35. See http://www.pcisig.com for complete specs
36. Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.
37. Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.
38. For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)2 = (total jitter)2 - (input jitter)2
39. Guaranteed by design and characterization, not tested in production
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