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PDF ( 数据手册 , 数据表 ) HCPL-0723

零件编号 HCPL-0723
描述 50 MBd 2 ns PWD High Speed CMOS Optocoupler
制造商 Avago
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HCPL-0723 数据手册, 描述, 功能
HCPL-7723/0723
50 MBd 2 ns PWD High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either 8-pin DIP or SO‑8 package style respec-
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize
the latest CMOS IC technology to achieve outs­tanding
speed performance of minimum 50 MBd data rate and
2 ns maximum pulse width distortion.
Basic building blocks of HCPL-7723/0723 are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver
IC, which supplies current to the LED. The detector
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with
an output driver.
Functional Diagram
**VDD1 1
8 VDD2**
Features
• +5 V CMOS compatibility
• High speed: 50 MBd min.
• 2 ns max. pulse width distortion
• 22 ns max. prop. delay
• 16 ns max. prop. delay skew
• 10 kV/µs min. common mode rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals:
UL recognized
– 5000 Vrms for 1 min. per UL1577 for HCPL-7723 for
option 020
– 3750 Vrms for 1 min. per UL1577 for HCPL-0723
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-5
– Viorm = 630 Vpeak for HCPL-7723   option 060
– Viorm = 567 Vpeak for HCPL-0723   option 060
VI 2
NC* 3
GND1 4
LED1
SHIELD
7 NC*
IO
6 VO
5 GND2
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
Applications
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
SDS, Isolated A/D or D/A conversion
• Multiplexed data transmission
• High speed digital input/output
• Computer peripheral interface
• Microprocessor system interface
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.







HCPL-0723 pdf, 数据表
Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter
Symbol Min. Typ.
Max. Units
Test Conditions
Propagation Delay Time to Logic
Low Output[3]
tPHL 16 22 ns CL = 15 pF CMOS Signal Levels; Figure 5
Propagation Delay Time to Logic
High Output[3]
tPLH 16 22 ns CL = 15 pF CMOS Signal Levels; Figure 5
Pulse Width
PW 20 ns CL = 15 pF CMOS Signal Levels
Maximum Data Rate
Pulse Width Distortion[4] |tPHL - tPLH|
|PWD|
Propagation Delay Skew[5] tPSK
50
MBd CL = 15 pF CMOS Signal Levels
1 2 ns CL = 15 pF CMOS Signal Levels; Figure 6
16 ns CL = 15 pF CMOS Signal Levels
Output Rise Time (10% – 90%)
tR 8 ns CL = 15 pF CMOS Signal Levels
Output Fall Time (90% - 10%)
tF 6 ns CL = 15 pF CMOS Signal Levels
Common Mode Transient Immunity
|CMH| 10 15 kV/µs VCM = 1000 V, TA = 25°C,
at Logic High Output[6] VI = VDD1, VO > 0.8 VDD2
Common Mode Transient Immunity
|CML| 10 15 kV/µs VCM = 1000 V, TA = 25°C,
at Logic Low Output[6] VI = 0 V, VO < 0.8 V
8














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