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PDF ( 数据手册 , 数据表 ) 74LVC126A

零件编号 74LVC126A
描述 Quad buffer/line driver
制造商 NXP Semiconductors
LOGO NXP Semiconductors LOGO 


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74LVC126A 数据手册, 描述, 功能
74LVC126A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 8 — 8 April 2014
Product data sheet
1. General description
The 74LVC126A consists of four non-inverting buffers/line drivers with 3-state outputs,
which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs
to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC126AD 40 C to +125 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC126ADB 40 C to +125 C SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
74LVC126APW 40 C to +125 C TSSOP14 plastic thin small outline package; 14 leads;
body width 4.4 mm
74LVC126ABQ 40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1







74LVC126A pdf, 数据表
NXP Semiconductors
74LVC126A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
tW
VM
tr
tf
VM
VI
G
VCC
DUT
VO
VEXT
RL
RT CL RL
001aae331
Fig 8.
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Test circuit for measuring switching times
Table 9. Test data
Supply voltage
1.2 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
Input
VI
VCC
VCC
VCC
2.7 V
2.7 V
tr, tf
2 ns
2 ns
2 ns
2.5 ns
2.5 ns
Load
CL
30 pF
30 pF
30 pF
50 pF
50 pF
RL
1 k
1 k
500
500
500
VEXT
tPLH, tPHL
open
open
open
open
open
tPLZ, tPZL
2 VCC
2 VCC
2 VCC
2 VCC
2 VCC
tPHZ, tPZH
GND
GND
GND
GND
GND
74LVC126A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 8 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 16







74LVC126A equivalent, schematic
NXP Semiconductors
74LVC126A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 April 2014
Document identifier: 74LVC126A










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