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PDF ( 数据手册 , 数据表 ) 93C66

零件编号 93C66
描述 3-Wire Serial EEPROM
制造商 FMD
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93C66 数据手册, 描述, 功能
Fremont Micro Devices
3-Wire Serial EEPROM
1K, 2K and 4Kbit (8-bit or 16-bit wide)
93C46/A, 93C56/A, 93C66/A
FEATURES
Standard Voltage and Low Voltage Operation:
FT93C46/56/66:
VCC = 2.5V to 5.5V
FT93C46A/56A/66A:
VCC = 1.8V to 5.5V
User Selectable Internal Organization:
FT93C46: 128 x 8 or 64 x 16
FT93C56: 256 x 8 or 128 x 16
FT93C66: 512 x 8 or 256 x 16
2 MHz Clock Rate (5V) Compatibility.
Industry Standard 3-wire Serial Interface.
Self-Timed ERASE/WRITE Cycles (5ms max including auto-erase).
Automatic ERAL before WRAL.
Sequential READ Function.
High Reliability: Typical 1 Million Erase/Write Cycle Endurance.
100 Years Data Retention.
Industrial Temperature Range (-40o C to 85o C).
Standard 8-pin PDIP/SOIC/TSSOP Pb-free Packages.
DESCRIPTION
The FT93C46/56/66 series are 1024/2048/4096 bits of serial Electrical Erasable and Programmable
Read Only Memory, commonly known as EEPROM. They are organized as 64/128/256 words of 16 bits
each when the ORG pin is connected to VCC (or unconnected) and 128/256/512 words of 8 bits (1 byte)
each when the ORG pin is tied to ground. The devices are fabricated with proprietary advanced CMOS
process for low power and low voltage applications. These devices are available in standard 8-lead
PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages. Our extended VCC range (1.8V to 5.5V)
devices enables wide spectrum of applications.
The FT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial
interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SCL). Upon receiving a READ
instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO.
The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The
WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. Once a device
begins its self-timed program procedure, the data out pin (DO) can indicate the READY/BUSY status by
rising chip select (CS).
© 2013 Fremont Micro Devices Inc.
Confidential Rev. 0.8
DS93CXX-A-page1







93C66 pdf, 数据表
Fremont Micro Devices
WRAL Timing (2)
CS
SCL
DI
93C46/A, 93C56/A, 93C66/A
x x Dn Dn+1
D1 D0
DO
Note :
START
BIT
OP
CODE
ADDR
1. Valid only at VCC=4.5V to 5.5V
2. Valid only at VCC=4.5V to 5.5V
DATA IN
Twc
Synchronous Data Timing
CS VIH
VIL
SCL VIH
VIL
DI VIH
VIL
DO VIH
( read ) VIL
DO VIH
( program ) VIL
t CSS
t SCLH
t DIS t DIH
t PD0
t SV
t SCLL
t PD1
STATUS
VALID
t CSH
t DF
t DF
© 2013 Fremont Micro Devices Inc.
Confidential Rev. 0.8
DS93CXX-A-page8







93C66 equivalent, schematic
Fremont Micro Devices
93C46/A, 93C56/A, 93C66/A
Density
Package
Temperature
Range
Pin and
Voltage
0-70
1.8V-5.5V
2.5V-5.5V
1.8V-5.5V
-40-85
2.5V-5.5V
2kbits
DIP8
0-70
1.8V-5.5V
2.5V-5.5V
-40-851.8V-5.5V
HSF
RoHS
Green
RoHS
Green
RoHS
Green
RoHS
Green
RoHS
Green
RoHS
Green
RoHS
Green
Packaging
Tube
Tube
Tube
Tube
Tube
Tube
Tube
Tube
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
Tube
Tape and Reel
SOP8
-40-85
2.5V-5.5V
RoHS
Green
Tube
Tape and Reel
Tube
Tape and Reel
Ordering Code
FT93C56A-CDR-B
FT93C56A-CDG-B
FT93C56-CDR-B
FT93C56-CDG-B
FT93C56A-IDR-B
FT93C56A-UDR-B
FT93C56A-IDG-B
FT93C56A-UDG-B
FT93C56-IDR-B
FT93C56-UDR-B
FT93C56-IDG-B
FT93C56-UDG-B
FT93C56A-CSR-B
FT93C56A-CSR-T
FT93C56A-CSG-B
FT93C56A-CSG-T
FT93C56-CSR-B
FT93C56-CSR-T
FT93C56-CSG-B
FT93C56-CSG-T
FT93C56A-ISR-B
FT93C56A-USR-B
FT93C56A-ISR-T
FT93C56A-USR-T
FT93C56A-ISG-B
FT93C56A-USG-B
FT93C56A-ISG-T
FT93C56A-USG-T
FT93C56-ISR-B
FT93C56-USR-B
FT93C56-ISR-T
FT93C56-USR-T
FT93C56-ISG-B
FT93C56-USG-B
FT93C56-ISG-T
FT93C56-USG-T
© 2013 Fremont Micro Devices Inc.
Confidential Rev. 0.8
DS93CXX-A-page16










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