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PDF ( 数据手册 , 数据表 ) KLI-8023

零件编号 KLI-8023
描述 Linear CCD Image Sensor
制造商 ON Semiconductor
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KLI-8023 数据手册, 描述, 功能
KLI-8023
Linear CCD Image Sensor
Description
The KLI−8023 Image Sensor is a multispectral, linear solid state
image sensor for color scanning applications where ultra-high
resolution is required.
The imager consists of three parallel linear photodiode arrays, each
with 8,000 active photosites for the output of red, green, and blue
(R, G, B) signals. This device offers high sensitivity, high data rates,
low noise and negligible lag. Individual electronic exposure control
for each color allows the KLI−8023 sensor to be used under a variety
of illumination conditions. The imager can be operated in an Extended
Dynamic Range mode for the most demanding applications.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
3 Channel, RGB Trilinear CCD
Pixel Count
8002 × 3
Pixel Size
9 mm (H) × 9 mm (V)
Pixel Pitch
9 mm
Inter-Array Spacing
108 mm (12 Lines Effective)
Imager Size
Saturation Signal
72.0 mm (H) × 0.225 mm (V)
185 ke(Normal DR Mode)
400 ke(Extended DR Mode)
Dynamic Range
(2 MHz Data Rate)
84 dB (Normal DR Mode)
90 dB (Extended DR Mode)
Responsivity
R, G, B (−RAA)
R, G, B (−DAA)
Mono (−AAA, −SAA, −MAA)
Output Sensitivity
32, 20, 20 V/mJ/cm2
29, 19, 18 V/mJ/cm2
33 V/mJ/cm2
14.4 mV/e
Dark Current
0.002 pA/Pixel
Dark Current Doubling Rate
8°C
Charge Transfer Efficiency
0.999998/Transfer
Photoresponse Non-Uniformity
3% Peak-Peak
Lag (First Field)
0.025%
Maximum Data Rate
6 MHz/Channel
Package
CERDIP (Sidebrazed, CuW)
Cover Glass
AR Coated, 2 Sides
NOTE: Parameters above are specified at T = 25°C (junction temperature) and
1 MHz clock rates unless otherwise noted.
www.onsemi.com
Figure 1. KLI−8023 Linear CCD
Image Sensor
Features
12 Line Spacing between Color Channels
Single Shift Register per Channel
High Off-Band Spectral Rejection
Dark Reference Pixels Provided
Anti-Reflective Glass
Wide Dynamic Range, Low Noise
Dual Dynamic Range Mode Operation
No Image Lag
Electronic Exposure Control
High Charge Transfer Efficiency
Two-Phase Register Clocking
74 ACT Logic Compatible Clocks
6 MHz Maximum Data Rate
Applications
Digitization
Medical Imaging
Photography
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 2
1
Publication Order Number:
KLI−8023/D







KLI-8023 pdf, 数据表
Physical Description
Pin Description and Device Orientation
KLI−8023
SUB
f2A
SUB
SUB
SUB
LOGG
LOGB
LS
TG2
SUB
1
2
3
4
5
6
7
8
9
10
40 SUB
39 f1A
38 SUB
37 N/C
36 IG
35 ID
34 LOGR
33 SUB
32 TG1
31 SUB
SUB
fR
VSSB
VIDB
SUB
VIDG
VSSG
SUB
f1B
SUB
11
12
13
14
15
16
17
18
19
20
30 SUB
29 RD
28 OG
27 SUB
26 VDD
25 VIDR
24 VSSR
23 SUB
22 f2B
21 SUB
Figure 3. KLI−8023 Pinout
www.onsemi.com
8







KLI-8023 equivalent, schematic
KLI−8023
REFERENCE DESIGN CIRCUIT OVERVIEW
Programmable Logic
See the timing waveform requirements earlier in this
document before programming a logic device.
Clock Drivers
There are three types of clock drivers (voltage translating
buffers) used in this reference design. The most important
performance consideration is the ability of the clock driver
to drive the capacitive loads presented by the various gates
of the CCD.
Reset Driver
The RESET, (fR), gate presents a small capacitive load
of 100 pF, and requires fast rise and fall times.
The complimentary bipolar switching transistor circuit
shown in Figure 12 provides a low cost solution. The circuit
alternately drives the PNP and NPN transistors into
saturation, which switches the output between VCC and
ground. A 33-W series-damping resistor is used to suppress
ringing.
Exposure Control and Transfer Gates
The exposure control gates; LOGR and LOGG, and the
transfer gates; TG1 and TG2 each present a moderate
capacitive load of 500 pF. The Elantec 7202 Dual-Channel
Power MOSFET driver delivers a peak output current of
2 amperes: more than enough to meet the rise and fall
requirements of the LOG and TG gates. Series damping
resistors are used to prevent ringing in the LOGR and LOGG
gates. The transfer gates are connected together and driven
by a single EL7202.
CCD Shift Register Driver
The CCD clock phases (f1A, f2A, f1B and f2B) present
a significant load of 3,100 pF per phase. Two 74ACT11244
octal buffers provide an efficient solution. Each clock phase
is driven by four gates connected in parallel to increase
output drive current. The 6.5-volt swing required by the shift
register is obtained by setting VCC to 6.8 V. Series damping
resistors RD are used to suppress ringing of the clock signals.
Values for RD should be varied to eliminate ringing and
achieve 50% crossover between each pair of shift register
clocks.
Bias Supplies
VDD, RD and OG
VDD and VRD are supplied directly from the 15 V input
power supply and OG is supplied by a voltage divider.
The input power should be sufficiently filtered to prevent
noise from coupling into the output stage of the KLI−8013
through the VDD node. Current spikes in the VRD and VDD
nodes, due to switching of the on-chip reset FET, are
suppressed by the addition of a 0.1 mF decoupling capacitor
to ground at each node. The decoupling capacitors should be
located as close as possible to the pins of the CCD and should
have a solid connection to ground. OG is also decoupled to
suppress voltage spikes the output gate of the device.
The OG node draws negligible current.
OG, VSSR, VSSG, VSSB
A forward-biased diode provides an inexpensive and
reliable voltage source for all three VSS nodes.
The switching action of the reset FET of the output stage can
cause voltage spikes to occur on the VSS nodes.
A decoupling capacitor located as close as practical to each
VSS pin, and connected to a solid system ground, will
minimize voltage spiking. In high dynamic range systems,
crosstalk between VSS channels might present a noise
problem. A separate supply for each of the three VSS nodes
will minimize channel crosstalk if it proves to be a problem.
Output Buffers
An emitter follower circuit buffers each output channel.
The emitter follower provides a high impedance load to the
on-chip source follower output stage, and provides low
output impedance for driving the downstream analog signal
processing circuits. A 180-W resistor connected between the
base and emitter of the emitter follower uses the forward
biased base to emitter voltage drop to provide a constant
current load for the on-chip output stage.
www.onsemi.com
16










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