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PDF ( 数据手册 , 数据表 ) SC9256S

零件编号 SC9256S
描述 PLL FOR DIGITAL TUNING SYSTEM
制造商 Silan Semiconductors
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SC9256S 数据手册, 描述, 功能
SC9256
PLL FOR DIGITAL TUNING SYSTEM
DESCRIPTION
The SC9256 is phase-locked loop (PLL) LSIs for digital tuning
systems (DTS) with built in 2 modulus prescalers.
All functions ate controlled through 3 serial bus lines. These LSIs are
used to configure high-performance digital tuning system.
DIP-16-300-2.54
FEATURES
* Optimal for configuring digital tuning systems in high-fi tuners and
car stereos.
* Built-in prescalers. Operate at input frequency ranging from 30~150
MHz during FMIN input (with 2 modulus prescaler) and at
0.5~40MHz during AMIN input (with 2 modulus prescaler or direct
dividing).
* 16 bit programmable counter, dual parallel output phase
comparator, crystal oscillator and reference counter.
* 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be
used.
* 15 possible reference frequencies. ( When using 4.5MHz crystal)
* Built-in 20 bit general-purpose counter for such uses as measuring
intermediate frequencies (IFIN1 and IFIN2)
* High-precision (±0.55~±7.15µs) PLL phase error detection.
* Numerous general-purpose I/O pins for such uses as peripheral
circuit control.
* All functions controlled through 3 serial bus lines.
*CMOS structure with operating power supply range of
VDD=5.0±0.5V.
SOP-16-300-1.27
* 3 N-channel open-drain output
ports (OFF withstanding voltage:
12V) for such uses as control
signal output.
* Standby mode function (turns off
FM, AM and IF amps) to save
current consumption.
ORDERING INFORMATION
Device
SC9256
SC9256S
Package
DIP-16-300-2.54
SOP-16-300-1.27
BLOCK DIAGRAM
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 1 of 22







SC9256S pdf, 数据表
SC9256
LSB
Address D0H
MSB
OSC1 OSC2
OSC1
0
1
0
1
OSC2
0
0
1
1
OSCILLATOR
FREQUENCY
3.6MHz
4.5MHz
7.2MHz
10.8MHz
XT
C X'tal
Divider
XT
C C=30pF Typ.
Fig.2
Note: set to 3.6MHz (OSC1=”0”and OSC2=”0”) when power is turned on. The crystal is not oscillating at this
time because the system is in standby mode.
Reference counter (Reference frequency divider)
The reference counter section consists of a crystal oscillator and a counter.
A crystal oscillator frequency of 3.6MHZ, 7.2MHZ or 10.8MHZ can be selected .A maximum of 15 reference
frequencies can be generated.
1. Setting reference frequency
The reference frequency is set using bits R0~R3.
LSB
Address D0H
R0 R1 R2 R3
MSB
R0 R1 R2 R3
REFERENCE
FREQUENCY
0000
0.5 KHz
1000
1 KHz
0100
2.5 KHz
1100
3 KHz
0010
3.125 KHz
1 0 1 0 *3.90654 KHz
0110
5 KHz
1110
6.25 KHz
R0 R1 R2 R3
REFERENCE
FREQUENCY
0001
*7.8125 KHz
1001
9 KHz
0101
10 KHz
1101
12.5 KHz
0011
25 KHz
1011
50 KHz
0111
100 KHz
1 1 1 1 Standby mode (*1)
Note: 1. Reference frequencies marked with an asterisk “*”can only be generated with a 4.5MHZ crystal oscillator.
2. (*1)Standby mode
Standby mode occurs when bits R0,R1,R2,and R3 are all set to “1”.In standby mode, the programmable
counter stops, and FM, AM and IFIN(when selected IFIN) are set to “amp off”state (pins at “L”level). This
saves current consumption when the radio is turned off. The DO pins become high impedance during
standby mode.
During standby mode, the I/O ports (I/O-5~I/O-6) and output ports (OT1~OT4) can be controlled and the
crystal oscillator can be turned on and off.
3.The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not
oscillating and the I/O ports are set to input mode.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 8 of 22







SC9256S equivalent, schematic
SC9256
Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock
F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of
the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a
time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference
frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked
state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is
reset every time the input register (D2H) reset bit is set to “1”, and set to “1”through the lock detection
timing. That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”.
Reference frequency
Programmable
counter output
DO output
Phase comparator
Lock detection strobe
Unlock is reset (RESET)
Unlock F/F (UNLOCK)
Lock enable (ENABLE)
Phase error detection
Counts phase difference.
Fig.10
High impedance
"L" level
"H" level
LSB
Address D2H
LSB
Address D3H
ENA- UN
BLE LOCK
RESET
MSB
Input register
Setting data to "1" resets unlock detection bit and lock enable bit.
MSB
Output register
1 PLL lock detection enabled
PLL lock detection in waiting
0 state
1 PLL in unlocked state(*)
0 PLL in locked state
Note: The asterisk (*) indicates an error state of over 180° phase difference relative to the reference frequency
2. Phase error detection bits (PE1~PE3)
The unlock bit detects, using the reference frequency cycle, the phase difference between the reference
frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1~PE3)
are capable of precise phase error detection of ±0.55µs~±7.15µs using the reference frequency cycle.( If the
UNLOCK bit is set to “1”and the phase difference relative to the reference frequency is over 180°, bits
PE1~PE3 cannot correctly detect the phase error. Therefore, bits PE1~PE3 are normally used when the
UNLOCK bit is set to “0”.) Bits PE1~PE3 detect phase error normally when the phase difference is -180°~180°
relative to the reference frequency cycle.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 16 of 22










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