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PDF ( 数据手册 , 数据表 ) AP0101CS

零件编号 AP0101CS
描述 High-Dynamic Range (HDR) Image Signal Processor
制造商 ON Semiconductor
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AP0101CS 数据手册, 描述, 功能
AP0101CS HDR: Image Signal Processor (ISP)
Features
AP0101CS High-Dynamic Range (HDR)
Image Signal Processor (ISP)
AP0101CS Datasheet, Rev. 7
For the latest product datasheet, please visit www.onsemi.com
Features
• Supports ON Semiconductor sensors with up to
1.2 Mp (1280x960)
• 45 fps at 1.2 Mp, 60 fps at 720p
• Optimized for operation with HDR sensors
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz flicker
avoidance
• Adaptive Local Tone Mapping (ALTM)
• Test Pattern Generator
• Two-wire serial programming interface
• Interface to low-cost Flash or EPROM through SPI
bus (to configure and load patches)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Dual Band IR filter support
Applications
• SMPTE296 HDCCTV cameras
• Surveillance network IP cameras
Table 1:
Key Performance Parameters
Parameter
Value
Primary camera
interface
Parallel
Primary camera input
format
Output interface
RAW12 Linear/Companded Bayer
data
Up to 20-bit Parallel1
Output format
YUV422 8-bit,10-bit, and
SMPTE296M
10-, 12-bit tone-mapped Bayer
Maximum resolution 1280x960 (1.2 Mp)
Input clock range2
6-30 MHz
Maximum frame rate3 45 fps at 1.2 Mp, 60 fps at 720p
Maximum output clock
frequency
Parallel clock up to 84 MHz
VDDIO_S 1.8 or 2.8 V nominal
Supply VDDIO_H
voltage VDD_REG
2.5 or 3.3 V nominal
1.8V nominal
VDDIO_OTPM 2.5 or 3.3 V nominal
Operating temperature
(ambient - TA)
–30°C to +70°C
Typical power
consumption4
130 mW
Notes: 1. 20-bit in one pixel clock format is only available in
SMPTE mode with the use of 4 GPIOs.
2. With input clock below 10 MHz, the two wire
serial interface is supported only up to 100 KHz
3. Maximum frame rate depends on output inter-
face and data format configuration used.
4. 720p HDR 60 fps 74.25 MHz YCbCr_422_16
AP0101CS/D Rev. 7, 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,







AP0101CS pdf, 数据表
AP0101CS HDR: Image Signal Processor (ISP)
System Interfaces
Table 4: Pin Descriptions (Continued)
Name
SPI_SDI
SPI_SDO
SPI_CS_BAR
FV_OUT
LV_OUT
PIXCLK_OUT
DOUT[15:0]
GPIO [5:1]
TRST_BAR
EXT_CLK_OUT
RESET_BAR_OUT
M_SCLK
M_SDATA
FV_IN
LV_IN
PIXCLK_IN
DIN[11:0]
TRIGGER_OUT
VDDIO_S
GND
VDD_REG
LDO_OP
FB_SENSE
GND_REG
VDD_PLL
VDD
VDDIO_OTPM
VDDIO_H
Type
Input
Output
Output
Output
Output
Output
Output
I/O
Input
Output
Output
Output
I/O
Input
Input
Input
Input
Output
Supply
Supply
Supply
Output
Input
Supply
Supply
Supply
Supply
Supply
Description
Data in from SPI flash or EEPROM memory. When no SPI device is fitted, this signal is
used to determine whether the AP0101CS should auto-configure:
0: Do not auto-configure; two-wire interface will be used to configure the device (host-
config mode)
1: Auto-configure.
This signal has an internal pull-up resistor.
Data out to SPI flash or EEPROM memory.
Chip select out to SPI flash or EEPROM memory.
Host frame valid output (synchronous to PIXCLK_OUT)
Host line valid output (synchronous to PIXCLK_OUT)
Host pixel clock output.
Host pixel data output (synchronous to PIXCLK_OUT) DOUT[15:0].
Note 20-bit output (SMPTE) also uses GPIO[5:2].
General purpose digital I/O.
Note: 20-bit output (SMPTE) also uses GPIO[5:2]
Must be tied to GND in normal operation.
Clock to external sensor.
Reset signal to external sensor.
Two-wire serial interface clock (Master).
Two-wire serial interface clock (Master).
Sensor frame valid input.
Sensor line valid input.
Sensor pixel clock input.
Sensor pixel data input DIN[11:0]
Trigger signal for external sensor.
Sensor I/O power supply.
Ground for sensor IO, host IO, PLL, VDDIO_OTPM, and VDD.
Input to on-chip 1.8V to 1.2V regulator.
Output from on-chip 1.8V to 1.2V regulator.
Note: The regulator on the AP0101CS must be used.
On-chip regulator sense signal.
Ground for on-chip regulator
PLL supply.
Core supply.
OTPM power supply.
Host I/O power supply.
AP0101CS/D Rev. 7, 1/16 EN
8 ©Semiconductor Components Industries, LLC,2016.







AP0101CS equivalent, schematic
Figure 9: AP0101CS IFP
AP0101CS HDR: Image Signal Processor (ISP)
Image Flow Processor
linear or
com panded data
AE,FD and ALTM
stats
RAW 12- or 20-bit Bayer
12-bit ALTM Bayer
R X D efect correctio,n
decompanding N oise reduction
Black level
s ubtr ac ti o,n
D igital gain
control,PGA
ALTM
C olor
Interpolation
C olor
Correction
Aperture
Correction
C r op
Gamma
R GB 2YU V
Color Kill
YUV
filters
Scaler
Progressive
Test pattern
generator
AW B stats
RAW Bayer
ALTM Bayer
RGB
YCbCr
Progressive parallel or SMPTE
(YCbCr or
Bayer)
AP0101CS/D Rev. 7, 1/16 EN
16
©Semiconductor Components Industries, LLC,2016.










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