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PDF ( 数据手册 , 数据表 ) GD25LQ32C

零件编号 GD25LQ32C
描述 1.8V Uniform Sector Dual and Quad Serial Flash
制造商 GigaDevice
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GD25LQ32C 数据手册, 描述, 功能
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32C
GD25LQ32C
DATASHEET
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GD25LQ32C pdf, 数据表
1.8V Uniform Sector
Dual and Quad Serial Flash
4. DEVICE OPERATION
GD25LQ32C
SPI Mode
Standard SPI
The GD25LQ32C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25LQ32C supports Dual SPI operation when using the Dual Output Fast Readand Dual I/O Fast Read
(3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25LQ32C supports Quad SPI operation when using the Quad Output Fast Read,Quad I/O Fast Read,
Quad I/O Word Fast Read, “Quad Page Program” (6BH, EBH, E7H, 32H) commands. These commands allow data to be
transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and
SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI
commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
QPI
The GD25LQ32C supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)command. The QPI mode utilizes all four IO
pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be
active at any given times. Enable the QPI (38H)and Disable the QPI (FFH)” commands are used to switch between
these two modes. Upon power-up and after software reset using “”Reset (99H)command, the default state of the device is
Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesnt stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK dont care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
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GD25LQ32C equivalent, schematic
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32C
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,)
IO1 = (x, x, x, x, D5, D1,)
IO2 = (x, x, x, x, D6, D2,)
IO3 = (x, x, x, x, D7, D3,)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,)
IO1 = (x, x, D5, D1,)
IO2 = (x, x, D6, D2,)
IO3 = (x, x, D7, D3,)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address.
9. QPI Command, Address, Data input/output format:
CLK #0 1 2 3 4 5 6 7 8 9 10 11
IO0= C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0,
IO1= C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2= C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3= C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
10. Read Serial Flash Discoverable Parameter (SFDP) command is available on special order. Please contact GigaDevice
if this function is needed.
Table of ID Definitions:
GD25LQ32C
Operation Code
9FH
90H
ABH
M7-M0
C8
C8
ID15-ID8
60
ID7-ID0
16
15
15
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