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PDF ( 数据手册 , 数据表 ) GD25D10B

零件编号 GD25D10B
描述 Uniform Sector Standard and Dual Serial Flash
制造商 GigaDevice
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GD25D10B 数据手册, 描述, 功能
Uniform Sector
Standard and Dual Serial Flash
GD25D10B/05B
GD25D10B/05B
DATASHEET
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GD25D10B pdf, 数据表
Uniform Sector
Standard and Dual Serial Flash
5. DATA PROTECTION
GD25D10B/05B
The GD25D10B/05B provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
reset to 0 in the following situations:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected memory
area which is read-only and unalterable.
Hardware Protection Mode: WP# going low to protected the BP0~BP2bits and SRP bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.
Status Register Content
BP2 BP1 BP0
000
001
010
011
100
101
11X
Table1.0(a) GD25D10B Protected area size
Memory Content
Blocks
Addresses
Density
NONE
Sector 0 to 29
Sector 0 to 27
Sector 0 to 23
Sector 0 to 15
All
All
NONE
000000H-01DFFFH
000000H-01BFFFH
000000H-017FFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-01FFFFH
NONE
120KB
112KB
96KB
64KB
128KB
128KB
Portion
NONE
Lower 30/32
Lower 28/32
Lower 24/32
Lower 16/32
ALL
ALL
Status Register Content
BP2 BP1 BP0
000
001
010
011
1XX
Table1.0(b) GD25D05B Protected area size
Memory Content
Blocks
NONE
Sector 0 to 29
Sector 0 to 27
Sector 0 to 23
All
Addresses
NONE
000000H-00DFFFH
000000H-00BFFFH
000000H-007FFFH
000000H-00FFFFH
Density
NONE
56KB
48KB
32KB
64KB
Portion
NONE
Lower 14/16
Lower 12/16
Lower 8/16
ALL
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GD25D10B equivalent, schematic
Uniform Sector
Standard and Dual Serial Flash
GD25D10B/05B
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Fast Page Program (FPP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Fast Page Program (FPP) command is not executed when it is applied to a page protected by the Block Protect
(BP2, BP1, BP0).
Figure 9. Fast Page Program Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SI
CS#
SCLK
Command
F2H
24-bit address
Data Byte 1
23 22 21
321076543210
MSB
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
SI
7654321076543210
76543210
MSB
MSB
MSB
7.11. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the specific sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure10. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP2, BP1, BP0) bit (see Table1.0&1.1) is not executed.
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