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PDF ( 数据手册 , 数据表 ) LV5213LP

零件编号 LV5213LP
描述 3ch LED Driver
制造商 ON Semiconductor
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LV5213LP 数据手册, 描述, 功能
Ordering number : ENA0183A
LV5213LP
Bi-CMOS LSI
3ch LED Driver
http://onsemi.com
Overview
This LV5213LP is LED driver for cell phones. Each LED driver gets a constant current controlled. The brilliance
control becomes possible by changing the current value that flows to LED by the serial bus control.
LV5213LP can achieve various effects of the illumination of a full-color LED display.
Functions
Three color LED driver circuits.
The LED current can be switched independently in 5-bit units (0 to 5mA).
Independent on/off control of the three LED drivers (independent control of the 3 RGB colors).
Each LED drive current level can be adjusted independently over the serial bus.
Miniature package.
Thermal shutdown circuit.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Supply voltage 1
Supply voltage 2
Allowable power dissipation
VCC max
VDD max
Pd max
Mounted on the specified board *
Maximum input current
Maximum output current
STBY pin voltage
Operating temperature
VINB
IO max
VSTBY
Topr
Storage temperature
Tstg
The specified board *: 50mm × 40mm × 0.8mm glass epoxy (4-layer circuit board).
Ratings
6.0
6.0
5.5
6.0
12.0
6.0
-30 to +75
-40 to +125
Unit
V
V
W
V
mA
V
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
August, 2013
O0610 SY/D1405 MS OT 20051201-S00002 No.A0183-1/10







LV5213LP pdf, 数据表
Serial Data Transfer Timing Conditions
LV5213LP
Parameter
Cycle time
Data setup time
Data hold time
Pulse width
Symbol
tcy1
ts0
ts1
th0
th1
tw1L
tw1H
tw2L
Conditions
SCLK clock period
The CS setup time from the SLCK rising edge
The SDATA setup time from the SLCK rising edge
The CS hold time from the SLCK falling edge
The SDATA hold time from the SCLK rising edge
SCLK low period pulse width
SCLK high period pulse width
CS low period pulse width
min
330
150
100
300
100
150
150
1.0
typ
max unit
nS
nS
nS
nS
nS
nS
nS
μS
Data length:
Clock frequency:
16bits
Up to 2MHz
After 16 clock cycles have been input with CS at the high level, SDATA is acquired on the fall of CS.
Note: SDATA will not be acquired if 15 or fewer clock cycles were input during the CS high-level period. If 17 or more
clock cycles are input, the SDATA for the first 16 cycles are acquired and the SDATA following those 16 cycles is
ignored.
Power Supply Application
1. Either bring up VCC and VDD at the same time, or bring up VCC first then VDD.
2. Then, set the serial data. (After the serial data has been set, a period of about 2µs is required as the startup time for
the IC internal circuits.)
3. Finally, clear the STBY pin states.
No.A0183-8/10














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