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PDF ( 数据手册 , 数据表 ) DAC1201D125

零件编号 DAC1201D125
描述 Dual 12-bit DAC
制造商 NXP Semiconductors
LOGO NXP Semiconductors LOGO 


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DAC1201D125 数据手册, 描述, 功能
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
Rev. 2 — 27 January 2012
Product data sheet
1. General description
The DAC1201D125 is a dual-port, high-speed, 2-channel CMOS Digital-to-Analog
Converter (DAC), optimized for high dynamic performance with low power dissipation.
Supporting an update rate of up to 125 Msps, the DAC1201D125 is suitable for Direct IF
applications.
Separate write inputs allow data to be written to the two DAC ports independently of one
another. Two separate clocks control the update rate of each DAC port.
The DAC1201D125 can interface two separate data ports or one single interleaved
high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its
original I and Q data and latched. The I and Q data is then converted by the two DACs
and updated at half the input data rate.
Each DAC port has a high-impedance differential current output, suitable for both
single-ended and differential analog output configurations.
The DAC1201D125 is pin compatible with the AD9765, DAC2902 and DAC5662.
2. Features and benefits
Dual 12-bit resolution
125 Msps update rate
Single 3.3 V supply
Dual-port or Interleaved data modes
1.8 V, 3.3 V and 5 V compatible digital
inputs
Internal and external reference
2 mA to 20 mA full-scale output current
Typical 185 mW power dissipation
16 mW power-down
SFDR: 81 dBc; fo = 1 MHz; fs = 52 Msps
SFDR: 78 dBc; fo = 10.4 MHz; fs = 78
Msps
SFDR: 74 dBc; fo = 1 MHz;
fs = 52 Msps; 12 dBFS
LQFP48 package
Industrial temperature range of
40 C to +85 C
3. Applications
Quadrature modulation
Medical/test instrumentation
Direct IF applications
Direct digital frequency synthesis
Arbitrary waveform generator







DAC1201D125 pdf, 数据表
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
80
SFDR
(dBc)
76
72
68
(1)
(2)
(3)
(4)
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64
60
20 0
20
60
T (°C)
(1) fo = 5 MHz
(2) fo = 10 MHz
(3) fo = 15 MHz
(4) fo = 20 MHz
Fig 3. SFDR as a function of the ambient temperature at 125 Msps
100
DAC1201D125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 27 January 2012
© NXP B.V. 2012. All rights reserved.
8 of 28







DAC1201D125 equivalent, schematic
NXP Semiconductors
DAC1201D125
Dual 12-bit DAC, up to 125 Msps
10.2.2 Interleaved mode
The data and clock circuit for Interleaved mode operation is illustrated in Figure 16.
DA11 to DA0
12 INPUT A 12
LATCH
DAC A
LATCH
IQWRT
IQSEL
IQCLK
IQRESET
12 INPUT B 12
LATCH
DAC B
LATCH
÷2
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Fig 16. Interleaved mode
In Interleaved mode, both DACs use the same data and clock inputs at twice the update
rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A
or latch B, depending on the value of IQSEL. The IQSEL transition must occur when
IQWRT and IQCLK are LOW.
The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is
updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see Figure 17.
DA11 to DA0/
DB11 to DB0
N N+1 N+2 N+3 N+4 N+5 N+6 N+7
IQSEL
IQWRT
IQCLK
IQRESET
IOUTAP, IOUTAN
XX
IOUTBP, IOUTBN
XX
Fig 17. Interleaved mode timing
N
N+1
N+4
N+2
N+3
N+5
001aaj116
DAC1201D125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 27 January 2012
© NXP B.V. 2012. All rights reserved.
16 of 28










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