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PDF ( 数据手册 , 数据表 ) LE25S81FD

零件编号 LE25S81FD
描述 8M-bit (1024K x 8) Serial Flash Memory
制造商 ON Semiconductor
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LE25S81FD 数据手册, 描述, 功能
Ordering number : EN*A2262A
LE25S81FD
Advance Information
CMOS LSI
8M-bit (1024K 8) Serial Flash Memory
http://onsemi.com
Overview
The LE25S81FD is a SPI bus flash memory device with a 8M bit (1024K 8-bit) configuration. It uses a single
1.8V power supply. While making the most of the features inherent to a serial flash memory device, the
LE25S81FD is housed in an 8-pin ultra-miniature package. All these features make this device ideally suited to
storing program in applications such as portable information devices, which are required to have increasingly
more compact dimensions. The LE25S81FD also has a small sector erase capability which makes the device ideal
for storing parameters or data that have fewer rewrite cycles and conventional EEPROMs cannot handle due to
insufficient capacity.
Function
Read/write operations enabled by single 1.8V power supply : 1.65 to 1.95V supply voltage range
Operating frequency
: 40MHz
Temperature range
: –40 to +90C
Serial interface
: SPI mode 0, mode 3 supported
Sector size
: 4K bytes/small sector, 64K bytes/sector
Small sector erase, sector erase, chip erase functions
Page program function (256 bytes / page)
Block protect function
Data retention period
: 20 years
Status functions
: Ready/busy information, protect information
Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ.), 150ms (max.)
Sector erase time
: 80ms (typ.), 250ms (max.)
Chip erase time
: 500ms (typ.), 6.0s (max.)
Page program time
: 0.3ms/256 bytes (typ.), 0.5ms/256 bytes (max.)
Package
: VSOIC8 NB, CASE 753AA
* This product is licensed from Silicon Storage Technology, Inc. (USA).
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of this data sheet.
Semiconductor Components Industries, LLC, 2014
April, 2014
VSOIC8 NB
42214HK/D1813HKPC No.A2262-1/23







LE25S81FD pdf, 数据表
LE25S81FD
Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
There are two read commands, the standard SPI read command and High-speed read command.
1-1. Read command
Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following
(03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 4-a Read"
shows the timing waveforms.
Figure 4-a Read
CS
SCK
SI
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47
8CLK
03h
Add. Add. Add.
N N+1 N+2
High Impedance
SO DATA DATA DATA
MSB MSB MSB
1-2. High-speed read command
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8 dummy
bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference.
"Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b High-speed Read
CS
SCK
SI
SO
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55
8CLK
MSB
0Bh
Add. Add. Add.
High Impedance
X
N N+1 N+2
DATA DATA DATA
MSB MSB MSB
No.A2262-8/23







LE25S81FD equivalent, schematic
LE25S81FD
11. ID Read
ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is not
accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID. In the
first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the subsequent
bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory type, memory
capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as clock inputs are
present, "Table 7-1 JEDEC ID codes table" lists the silicon ID codes and "Figure 16-a JEDEC ID read" shows the
JEDEC ID read timing waveforms.
The second method involves inputting the ID read command. This command consists of the first through fourth bus
cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID codes table"
lists the silicon ID codes and "Figure 16-b ID read" shows the ID read timing waveforms.
If the SCK input persists after a device code is read, that device code continues to be output. The data output is
transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence is
finished by setting CS high.
Table 7-1 JEDEC ID read
Manufacturer code
2 byte device ID
Memory type
Memory capacity code
Device code
1
Output code
62h
16h
14h (8M Bit)
00h
Table 7-2 ID read
Output Code
1 byte device ID
86h
(LE25S81FD)
Figure 16-a Silicon ID Read 1
CS
SCK
SI
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
8CL
9Fh
High Impedance
SO
Figure 16-b Silicon ID Read 2
62h 16h 14h 00h 62h
MSB MSB MSB MSB MSB
CS
SCK
SI
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39
8CL
ABh
X XX
High Impedance
SO 86h 86h
MSB MSB
No.A2262-16/23










页数 23 页
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