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零件编号 | UJA1061TW | ||
描述 | Low speed CAN/LIN system basis chip | ||
制造商 | Philips | ||
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DATA SHEET
UJA1061
Low speed CAN/LIN system
basis chip
Objective specification
2004 Mar 22
Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
6 FUNCTIONAL DESCRIPTION
6.1 Introduction
The UJA1061 combines all peripheral functions around a
microcontroller within typical automotive body multiplexing
applications into one dedicated chip. The functions are:
• Power supply for host microcontroller
• Power supply for CAN physical layer
• Switched BAT42 output
• System reset
• Watchdog with Window and Time-out modes
• On-chip oscillator
• Fault-tolerant CAN and LIN physical layers for serial
communication suitable for 12 and 42 V applications
• SPI control interface
• Local wake-up input
• Inhibit output, or ‘limp home’ output
• System Inhibit output port
• Compatibility with 42 V power supply systems
• Fail-safe behaviour.
6.2 Fail-safe system controller
The fail-safe system controller is the ‘heart’ of the
UJA1061 and is controlled mainly by the watchdog, which
is clocked directly via a dedicated, on-chip oscillator.
It handles the register configuration and controls all
internal functions of the UJA1061. The device status
information is collected and reflected to the
microcontroller. Also the reset and interrupt signals are
provided by the system controller.
The system controller is a state machine. The different
levels of operation provided are represented in Fig.3.
6.2.1 FAIL-SAFE MODE
During severe fault situations the UJA1061 always enters
its Fail-safe mode (see also Fig.3). This mode has the
lowest possible system power consumption. These fault
situations are:
• On-chip oscillator failure (frequency too low). Fail-safe
mode is entered from any other mode immediately after
this failure is detected
• Pin RSTN is clamped HIGH for more than 128 ms while
the UJA1061 tries to drive pin RSTN LOW. The
Fail-safe mode will be entered immediately out of any
other mode in which the UJA1061 tries to drive
pin RSTN LOW (Start-up, Standby or Sleep mode) after
detecting this failure
• Pin RSTN is clamped LOW for more than 256 ms after
the UJA1061 has released the pin RSTN internally in
Start-up or in Restart mode
• A falling edge on pin RSTN during the initialization
phase in Restart mode
• No successful initialization of Normal mode within
256 ms after pin RSTN has become HIGH in Restart
mode whereby that the software-controlled Software
Development mode is not active
• Wrong mode register code within Restart mode
• Wrong SPI count within Restart mode
• Low V1 regulator output for more than 256 ms due to a
too-high load or a short-circuit of V1 to ground in
Start-up mode
• Low V1 regulator output directly after an
already-released pin RSTN in Restart mode.
The following events cause the system to exit the Fail-safe
mode if the on-chip oscillator is running correctly:
• Activity on the CAN-bus
• Activity on the LIN-bus
• Activity on pin WAKE.
The UJA1061 restarts out of Fail-safe mode and enters
Start-up mode to give the application a new opportunity to
start. Regulator V1 starts again and the reset pulse will be
set to the long period (see Section 6.5.1).
6.2.2 START-UP MODE
Start-up mode is entered after a number of events that
result in a system reset (see Fig.3) and is the first
opportunity for the system to start-up. These events are:
• The first battery and ground connection of the module
whereby the power supply V1 for the host
microcontroller becomes active for the first time. The
UJA1061 provides a Power-on reset for the system. As
this is the first connection of the battery, the UJA1061
has no indication of the reset length required by the host
microcontroller, therefore the long reset sequence is
chosen as default
2004 Mar 22
8
Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
6.4.3 WATCHDOG TIME-OUT BEHAVIOUR
Whenever the UJA1061 operates in Standby mode, in
Sleep mode or in Flash mode, the watchdog is operated in
Time-out mode. The watchdog has to be triggered within
the actual programmed period time (see Fig.6). The
Time-out mode can be used to provide cyclic wake-up
events to the host microcontroller during Low-power
modes.
In Standby and in Flash mode the nominal periods can be
changed with any SPI access to the mode register. Since
in Sleep mode regulator V1 is off and the microcontroller is
not powered, no further change of the time-out period is
possible.
Any wrong mode register code access results in an
immediate system reset, entering Start-up mode.
6.4.4 WATCHDOG OFF BEHAVIOUR
Within Standby and Sleep mode, the watchdog OFF
behaviour can be selected in order to disable the watchdog
entirely.
If the watchdog is triggered with the watchdog OFF code
while the UJA1061 is in Standby Mode, or while the
UJA1061 enters Standby mode, the V1 current monitoring
function stays disabled for a period of time equal to the
previous or the default (4096 ms) watchdog period. The
default period is selected if the Standby mode is entered
directly with Watchdog OFF mode. After that period the
current monitoring is enabled. Then the behaviour of the
UJA1061 upon a too-high V1 current depends on the
setting of the V1CMC bit within the System Configuration
register. If bit V1CMC is set (reset option) a too-high V1
current causes immediately a reset. If bit V1CMC is not set
(watchdog restart option), the watchdog starts a new
period without the possibility to disable it except by
triggering it again with the watchdog OFF code. If the
watchdog OFF code is chosen the watchdog time-out
interrupt has no function. If the watchdog off behaviour has
been entered successfully and later on pin V1 current
increases again, the watchdog starts operating with the
previously programmed time-out period.
In case Standby mode is entered directly out of Normal
mode with watchdog off behaviour coding, the watchdog
keeps running with its maximum time period until pin V1
current falls below the threshold. If the current increases
again, the maximum period is used again.
If Sleep mode is entered together with the watchdog OFF
behaviour, the UJA1061 immediately forces pin RSTN to
LOW level. In parallel, pin V1 is disabled and the watchdog
is stopped.
handbook, full pagewidth
period
trigger range
time-out
trigger
via SPI
earliest
possible
trigger
point
trigger restarts period
(with different duration if
desired)
latest
possible
trigger
point
trigger range
new period
Fig.6 Watchdog triggering using Time-out mode.
time-out
MCE627
2004 Mar 22
16
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页数 | 30 页 | ||
下载 | [ UJA1061TW.PDF 数据手册 ] |
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