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PDF ( 数据手册 , 数据表 ) UJA1079TW

零件编号 UJA1079TW
描述 LIN core system basis chip
制造商 NXP Semiconductors
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UJA1079TW 数据手册, 描述, 功能
UJA1079
LIN core system basis chip
Rev. 02 — 27 May 2010
Product data sheet
1. General description
The UJA1079 core System Basis Chip (SBC) replaces the basic discrete components
commonly found in Electronic Control Units (ECU) with a Local Interconnect Network
(LIN) interface.
The UJA1079 supports the networking applications used to control power and sensor
peripherals by using the LIN interface as a local sub-bus.
The core SBC contains the following integrated devices:
LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with
LIN 1.3
Advanced independent watchdog (UJA1079/xx/WD versions)
250 mA voltage regulator for supplying a microcontroller; extendable with external
PNP transistor for increased current capability and dissipation distribution
Serial Peripheral Pnterface (SPI) (full duplex)
2 local wake-up input ports
Limp home output port
In addition to the advantages gained from integrating these common ECU functions in a
single package, the core SBC offers an intelligent combination of system-specific
functions such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Detailed status reporting on system and sub-system levels
The UJA1079 is designed to be used in combination with a microcontroller. The SBC
ensures that the microcontroller always starts up in a controlled manner.







UJA1079TW pdf, 数据表
NXP Semiconductors
UJA1079
LIN core system basis chip
from Standby or Normal
VBAT below
power-off threshold Vth(det)poff
(from all modes)
Overtemp
V1: OFF
limp home = LOW (active)
LIN: Off and
high resistance
watchdog: OFF
chip temperature above
OTP activatrion threshold Tth(act)otp
VBAT below
power-on threshold Vth(det)pon
Off
V1: OFF
LIN: Off and
high resistance
watchdog: OFF
INTN: HIGH
chip temperature below
OTP release threshold Tth(rel)otp
VBAT above
power-on threshold Vth(det)pon
watchdog overflow or
V1 undervoltage
watchdog
trigger
Standby
V1: ON
LIN: Lowpower/Off
watchdog: Timeout/Off
MC = 00
reset event or
MC = 00
MC = 10 or MC = 11
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
wake-up event if enabled
successful
watchdog
trigger
Normal
V1: ON
LIN: Active/Lowpower
watchdog: Window/
Timeout/Off
MC = 1x
Fig 3. UJA1079 system controller
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
Sleep
V1: OFF
LIN: Lowpower/Off
watchdog: OFF
RSTN: LOW
MC = 01
015aaa125
UJA1079_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
8 of 45







UJA1079TW equivalent, schematic
NXP Semiconductors
UJA1079
LIN core system basis chip
6.3 On-chip oscillator
The on-chip oscillator provides the timing reference for the on-chip watchdog and the
internal timers. The on-chip oscillator is supplied by an internal supply that is connected to
VBAT and is independent of V1.
6.4 Watchdog (UJA1079/xx/WD versions)
Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is
programmed via the NWP control bits in the WD_and_Status register (see Table 4). The
default watchdog period is 128 ms.
A watchdog trigger event is any write access to the WD_and_Status register. When the
watchdog is triggered, the watchdog timer is reset.
In watchdog Window mode, a watchdog trigger event within a closed watchdog window
(i.e. the first half of the window before ttrig(wd)1) will generate an SBC reset. If the watchdog
is triggered before the watchdog timer overflows in Timeout or Window mode, or within
the open watchdog window (after ttrig(wd)1 but before ttrig(wd)2), the timer restarts
immediately.
The following watchdog events result in an immediate system reset:
the watchdog overflows in Window mode
the watchdog is triggered in the first half of the watchdog period in Window mode
the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending
the state of the WDOFF pin changes in Normal mode or Standby mode
the watchdog mode control bit (WMC) changes state in Normal mode
After a watchdog reset (short reset; see Section 6.5.1 and Table 11), the default watchdog
period is selected (NWP = 100). The watchdog can be switched off completely by forcing
pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in
Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will
re-enable it.
Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is
pending. Any attempt to change WMC when an interrupt is pending will be ignored.
6.4.1 Watchdog Window behavior
The watchdog runs continuously in Window mode.
If the watchdog overflows, or is triggered in the first half of the watchdog period (less than
ttrig(wd)1 after the start of the watchdog period), a system reset will be performed.
Watchdog overflow occurs if the watchdog is not triggered within ttrig(wd)2 after the start of
watchdog period.
If the watchdog is triggered in the second half of the watchdog period (at least ttrig(wd)1, but
not more than ttrig(wd)2, after the start of the watchdog period), the watchdog will be reset.
The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode
and the watchdog mode control bit (WMC) is set to 0.
UJA1079_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
16 of 45










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