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PDF ( 数据手册 , 数据表 ) UJA1069TW24

零件编号 UJA1069TW24
描述 LIN fail-safe system basis chip
制造商 NXP Semiconductors
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UJA1069TW24 数据手册, 描述, 功能
UJA1069
LIN fail-safe system basis chip
Rev. 04 — 28 October 2009
Product data sheet
1. General description
The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components
which are common in every Electronic Control Unit (ECU) with a Local Interconnect
Network (LIN) interface. The fail-safe SBC supports all networking applications which
control various power and sensor peripherals by using LIN as a local sub-bus. The
fail-safe SBC contains the following integrated devices:
LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
Advanced independent watchdog
Dedicated voltage regulator for microcontroller
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Advanced fail-safe system behavior that prevents any conceivable deadlock
Detailed status reporting on system and sub-system levels
The UJA1069 is designed to be used in combination with a microcontroller and a LIN
controller. The fail-safe SBC ensures that the microcontroller is always started up in a
defined manner. In failure situations the fail-safe SBC will maintain the microcontroller
function for as long as possible, to provide full monitoring and software driven fall-back
operation.
The UJA1069 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.







UJA1069TW24 pdf, 数据表
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
mode change via SPI
mode change via SPI
watchdog
trigger
Standby mode
V1: ON
SYSINH: HIGH
LIN: off-line
watchdog: time-out/OFF
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
mode change via SPI
watchdog
trigger
Normal mode
V1: ON
SYSINH: HIGH
LIN: all modes available
watchdog: window
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
wake-up detected with its wake-up interrupt disabled
mode change via SPI
OR mode change to Sleep with pending wake-up
OR watchdog time-out with watchdog timeout interrupt disabled
OR watchdog OFF and IV1 > IthH(V1) with reset option
OR interrupt ignored > tRSTN(INT)
OR RSTN falling edge detected
flash entry enabled (111/001/111 mode sequence)
OR mode change to Sleep with pending wake-up
OR V1 undervoltage detected
OR illegal Mode register code
OR watchdog not properly served
OR interrupt ignored > tRSTN(INT)
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
Sleep mode
V1: OFF
SYSINH: HIGH/float
LIN: off-line
watchdog: time-out/OFF
INH/LIMP: LOW/float
RSTN: LOW
EN: LOW
init Normal mode
via SPI successful
Restart mode
V1: ON
SYSINH: HIGH
LIN: off-line
watchdog: start-up
INH/LIMP: LOW/float
EN: LOW
init Normal mode
via SPI successful
supply connected
for the first time
Start-up mode
V1: ON
SYSINH: HIGH
LIN: off-line
watchdog: start-up
INH/LIMP: HIGH/LOW/float
EN: LOW
t > tWD(init)
OR SPI clock count < > 16
OR RSTN falling edge detected
OR RSTN released and V1 undervoltage detected
OR illegal Mode register code
wake-up detected
AND oscillator ok
AND t > tret
wake-up detected
OR watchdog time-out
OR V3 overload detected
init Flash mode via SPI
AND flash entry enabled
leave Flash mode code
OR watchdog time-out
OR interrupt ignored > tRSTN(INT)
OR RSTN falling edge detected
OR V1 undervoltage detected
OR illegal Mode register code
t > tWD(init)
OR SPI clock count < > 16
OR RSTN falling edge detected
OR RSTN released and V1 undervoltage detected
OR illegal Mode register code
watchdog
trigger
Flash mode
V1: ON
SYSINH: HIGH
LIN: all modes available
watchdog: time-out
INH/LIMP: HIGH/LOW/float
EN: HIGH/LOW
Fail-safe mode
V1: OFF
SYSINH: HIGH/float
LIN: off-line
watchdog: OFF
INH/LIMP: LOW
RSTN: LOW
EN: LOW
oscillator fail
OR RSTN externally clamped HIGH detected > tRSTN(CHT)
OR RSTN externally clamped LOW detected > tRSTN(CLT)
OR V1 undervoltage detected > tV1(CLT)
from any
mode
001aad670
Fig 4. Main state diagram
UJA1069_4
Product data sheet
Rev. 04 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
8 of 64







UJA1069TW24 equivalent, schematic
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
V1 Vrel(UV)(V1)
Vdet(UV)(V1)
power-up
VRSTN
under-
voltage
missing
watchdog
access
under-
voltage
spike
power-
down
time
tRSTNL
Fig 7. Reset pin behavior
tRSTNL
tRSTNL
VRSTN
time
coa054
t RSTNL
RSTN
externally
forced LOW
VRSTN
t WD (init)
time
t RSTNL
RSTN externally forced LOW
time
t WD (init)
001aad181
Fig 8. Reset timing diagram
Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin
RSTN HIGH but pin RSTN level remains LOW for longer than tRSTN(CLT), the SBC
immediately enters Fail-safe mode since this indicates an application failure.
UJA1069_4
Product data sheet
Rev. 04 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
16 of 64










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