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PDF ( 数据手册 , 数据表 ) 34AA04

零件编号 34AA04
描述 EEPROM
制造商 Microchip
LOGO Microchip LOGO 


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34AA04 数据手册, 描述, 功能
34AA04
4K I2CSerial EEPROM with Software Write-Protect
Device Selection Table
Part
Number
VCC Max. Clock Temp
Range Frequency Ranges
34AA04
1.7-3.6
1 MHz(1)
I, E
Note 1: 400 kHz for 1.8V VCC < 2.2V
100 kHz for VCC < 1.8V
Features
• 4 Kbit EEPROM:
- Internally organized as two 256 x 8-bit banks
- Byte or page writes (up to 16 bytes)
- Byte or sequential reads within a single bank
- Self-timed write cycle (5 ms max.)
• JEDEC® JC42.4 (EE1004-v) Serial Presence
Detect (SPD) Compliant for DRAM (DDR4)
modules
• High-Speed I2C™ Interface:
- Industry standard 1 MHz, 400 kHz, and
100 kHz
- Schmitt Trigger inputs for noise suppression
- SMBus-compatible bus time out
- Cascadable up to eight devices
• Write Protection:
- Reversible software write protection for four
individual 128-byte blocks
• Low-Power CMOS Technology:
- Voltage range: 1.7V to 3.6V
- Write current: 1.5 mA at 3.6V
- Read current: 200 µA at 3.6V, 400 kHz
- Standby current: 1 µA at 3.6V
• High Reliability:
- More than one million erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-lead PDIP, SOIC, TSSOP, TDFN, and UDFN
Packages
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description
The Microchip Technology Inc. 34AA04 is a 4 Kbit
Electrically Erasable PROM which utilizes the I2C serial
interface and is capable of operation across a broad
voltage range (1.7V to 3.6V). This device is JEDEC
JC42.4 (EE1004-v) Serial Presence Detect (SPD)
compliant and includes reversible software write
protection for each of four independent 128 x 8-bit
blocks. The device features a page write capability of
up to 16 bytes of data. Address pins allow up to eight
devices on the same bus.
The 34AA04 is available in the 8-lead PDIP, SOIC,
TSSOP, TDFN, and UDFN packages.
Package Types
PDIP/SOIC/TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
TDFN/UDFN
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
Block Diagram
A0 A1 A2
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCC
VSS
HV Generator
Block 0
(000h-07Fh)
Block 1
(080h-0FFh)
Block 2
(100h-17Fh)
Block 3
(180h-1FFh)
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
2014 Microchip Technology Inc.
DS20005271B-page 1







34AA04 pdf, 数据表
34AA04
5.0 BANK ADDRESSING
To support backwards-compatibility with DDR2/3
(JEDEC EE1002) SPD EEPROMs, the memory array
of the 34AA04 is divided into two separate 256-byte
banks. The Set Bank Address (SBA) commands are
used to set the bank address to either 0 or 1. The
Read Bank Address (RBA) command is used to
determine which bank is currently selected.
Note 1: The bank address is volatile and is reset
to Bank 0 upon power-up.
2: The comparison between the A0, A1, and
A2 pins and the corresponding Chip
Select bits is disabled for Bank Select
commands.
Note: Sequential read operations cannot
cross a bank boundary and will roll over
back to the beginning of the selected
bank.
TABLE 5-1:
Bank
Bank 0
Bank 1
BANK ADDRESS RANGE
Logical Array Address
000h-0FFh
100h-1FFh
TABLE 5-2: BANK ADDRESSING INSTRUCTION SET
Control Byte
Function
Abbr
Control Code
Chip Select Bits R/W A0 Pin
Set Bank Address to 0
Set Bank Address to 1
Read Bank Address
SBA0
SBA1
RBA
Bit 7
0
Bit 6
1
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1100
101110
1101
0, 1, or VHV
0, 1, or VHV
0, 1, or VHV
5.1 Set Bank Address (SBA)
The Set Bank Address (SBA) commands are used to
select the array bank for future read and write
operations.
The master generates a Start condition followed by the
corresponding control byte for the chosen SBA
command (Table 5-2), with the R/W bit set to a logic
0’. Note that Chip Select bit A0 of the control byte
effectively determines which bank is selected. The
34AA04 will respond with an Acknowledge, and then
the master transmits two dummy bytes. The 34AA04
will not acknowledge either dummy byte. Finally, the
master generates a Stop condition to end the
operation (Figure 5-1).
Array Read and Write commands will operate in the
newly-selected bank until another SBA command is
executed, or the 34AA04 experiences a POR or BOR
event.
FIGURE 5-1: SET BANK ADDRESS
Bus Activity
Master
S
T
A
R
T
Control
Byte
Dummy
Byte
Dummy
Byte
S
T
O
P
SDA Line
S
0
1
1
0
1
1
A1
00
P
Bus Activity
A
C
K
Note 1: Chip Select bit A0 specifies which bank to select.
N
o
A
C
K
N
o
A
C
K
DS20005271B-page 8
2014 Microchip Technology Inc.







34AA04 equivalent, schematic
34AA04
FIGURE 9-1: SET WRITE PROTECTION
VHV
A0 Pin
Bus Activity
Master
S
T
A
R
T
Control
Byte
Dummy
Byte
Dummy
Byte
SDA Line
S
0
1
1
0
A1 A1 A1
210 0
Bus Activity
A2 A2
CC
KK
Note 1: Chip Select bits A0-A2 vary depending on which SWP command is being executed.
2: The 34AA04 will only acknowledge if the specified block is not currently write-protected.
S
T
O
P
P
A2
C
K
TABLE 9-3: DEVICE RESPONSE WHEN DEFINING WRITE PROTECTION
Status
Protected with SWPn
Not Protected
Command
SWPn
CWP
SWPn or CWP
ACK
NoACK
ACK
ACK
Address
Don’t Care
Don’t Care
Don’t Care
ACK
NoACK
ACK
ACK
Data Byte
Don’t Care
Don’t Care
Don’t Care
ACK Write Cycle
NoACK
No
ACK
Yes
ACK
Yes
9.2 Clear All Write Protection (CWP)
The Clear All Write Protection (CWP) command resets
all of the write protection in a single operation. It is
executed in the same manner as a SWP command,
except using the CWP control byte (Table 9-2).
The 34AA04 will always acknowledge and execute a
CWP command if an internal write cycle is not in
progress, regardless of the state of write protection.
9.3 Read Protection Status (RPS)
The Read Protection Status (RPS) commands provide
a way of determining whether or not the specified
block is currently write-protected.
Following the Start condition, the master transmits the
control byte for the desired RPS command (Table 9-2),
with the R/W bit set to logic ‘1’. If the specified block is
not write-protected, the 34AA04 will respond with an
Acknowledge signal. If the block is currently write-
protected, an Acknowledge will not be generated.
Regardless of the result, the master must read at least
one dummy byte from the 34AA04, transmitting a Not
Acknowledge signal after each byte, and generate a
Stop condition to end the command (Figure 9-3).
FIGURE 9-2: CLEAR ALL WRITE PROTECTION
VHV
A0 Pin
Bus Activity
Master
S
T
A
R
T
Control
Byte
Dummy
Byte
Dummy
Byte
S
T
O
P
SDA Line
S 0110 0110
P
Bus Activity
A AA
C CC
K KK
DS20005271B-page 16
2014 Microchip Technology Inc.










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