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PDF ( 数据手册 , 数据表 ) 11AA02E64

零件编号 11AA02E64
描述 EEPROM
制造商 Microchip
LOGO Microchip LOGO 


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11AA02E64 数据手册, 描述, 功能
11AA02E48/11AA02E64
2K UNI/O® Serial EEPROMs with EUI-48or EUI-64Node Identity
Device Selection Table
Part Number
Density
(bits)
11AA02E48
11AA02E64
2K
2K
VCC Range
1.8V-5.5V
1.8V-5.5V
Page Size
(Bytes)
16
16
Temp.
Ranges
I
I
Packages
SN, TT
SN, TT
Node Address
EUI-48
EUI-64
Features
• Pre-Programmed Globally Unique, 48-Bit or
64-Bit Node Address
• Compatible with EUI-48and EUI-64
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 µA standby current, maximum
• 256 x 8-Bit Organization
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Maximum Bit Rate – Equivalent to
100 kHz Clock Frequency
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write Enable Latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4,000V
• 3-Lead SOT-23 and 8-Lead SOIC Packages
• Pb-Free and RoHS Compliant
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C
Description
The Microchip Technology Inc.
11AA02E48/11AA02E64 (11AA02EXX(1)) device is a
2 Kbit Serial Electrically Erasable PROM. The device is
organized in blocks of x8-bit memory and support the
patented(2) single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
Note 1: 11AA02EXX is used in this document as
a generic part number for the 11AA02E48
and 11AA02E64 devices.
2: Microchip’s UNI/O® Bus products are
covered by the following patents issued
in the U.S.A.: 7,376,020 and 7,788,430.
Low-voltage design permits operation down to 1.8V,
with standby and active currents of only 1 µA and
1 mA, respectively.
The 11AA02EXX is available in standard 8-lead
SOIC and 3-lead SOT-23 packages.
Package Types (not to scale)
3-Lead SOT-23
(TT)
VSS 3
2 VCC
1 SCIO
SOIC
(SN)
NC 1
NC 2
NC 3
VSS 4
8 VCC
7 NC
6 NC
5 SCIO
Pin Function Table
Name
Function
SCIO
VSS
VCC
Serial Clock, Data Input/Output
Ground
Supply Voltage
2008-2016 Microchip Technology Inc.
DS20002122D-page 1







11AA02E64 pdf, 数据表
11AA02E48/11AA02E64
3.6 Device Standby
The 11AA02EXX features a low-power Standby mode
during which the device is waiting to begin a new
command. A high-to-low transition on SCIO will exit
low-power mode and prepare the device for receiving
the start header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK
(i.e., valid termination of a command)
• Reception of a standby pulse
Note:
In the case of the WRITE, WRSR, SETAL,
or ERAL commands, the write cycle is
initiated upon receipt of the NoMAK,
assuming all other write requirements
have been met.
3.7 Device Idle
The 11AA02EXX features an Idle mode during which
all serial data is ignored until a standby pulse occurs.
Idle mode will be entered upon the following
conditions:
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle
• Missed edge transition
• Reception of a MAK following a WREN, WRDI,
SETAL, or ERAL command byte
• Reception of a MAK following the data byte of a
WRSR command
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the slave, but will
prevent the slave from synchronizing properly with the
master. If the slave is not synchronized with the
master, an edge transition will be missed, thus causing
the device to enter Idle mode.
3.8 Synchronization
At the beginning of every command, the 11AA02EXX
utilizes the start header to determine the master’s bus
clock period. This period is then used as a reference for
all subsequent communication within that command.
The 11AA02EXX features re-synchronization circuitry
which will monitor the position of the middle data edge
during each MAK bit and subsequently adjust the
internal time reference in order to remain synchronized
with the master.
There are two variables which can cause the
11AA02EXX to lose synchronization. The first is
frequency drift, defined as a change in the bit
period, TE. The second is edge jitter, which is a single
occurrence change in the position of an edge within a
bit period, while the bit period itself remains constant.
3.8.1 FREQUENCY DRIFT
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some
tolerance for such frequency drift. The tolerance range
is specified by two parameters, FDRIFT and FDEV.
FDRIFT specifies the maximum tolerable change in bus
frequency per byte. FDEV specifies the overall limit in
frequency deviation within an operation (i.e., from the
end of the start header until communication is
terminated for that operation). The start header at the
beginning of the next operation will reset the
re-synchronization circuitry and allow for another FDEV
amount of frequency drift.
3.8.2 EDGE JITTER
Ensuring that edge transitions from the master always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization
circuitry is designed to provide some tolerance for edge
jitter.
The 11AA02EXX adjusts its phase every MAK bit, so
TIJIT specifies the maximum allowable peak-to-peak
jitter relative to the previous MAK bit. Since the position
of the previous MAK bit would be difficult to measure by
the master, the minimum and maximum jitter values for
a system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
The difference between the minimum and maximum
values, as a percentage of the bit period, should be
calculated and then compared against TIJIT to
determine jitter compliance.
Note:
Because the 11AA02EXX only
re-synchronizes during the MAK bit, the
overall ability to remain synchronized
depends on a combination of frequency
drift and edge jitter (i.e., if the MAK bit
edge is experiencing the maximum
allowable edge jitter, then there is no room
for frequency drift). Conversely, if the
frequency has drifted to the maximum
amount tolerable within a byte, then no
edge jitter can be present.
DS20002122D-page 8
2008-2016 Microchip Technology Inc.







11AA02E64 equivalent, schematic
11AA02E48/11AA02E64
5.0 DATA PROTECTION
The following protection has been implemented to
prevent inadvertent writes to the array:
• The Write Enable Latch (WEL) is reset on
power-up
• A Write Enable (WREN) instruction must be issued
to set the write enable latch
• After a write, ERAL, SETAL, or WRSR command,
the write enable latch is reset
• Commands to access the array or write to the
status register are ignored during an internal write
cycle and programming is not affected
6.0 POWER-ON STATE
The 11AA02EXX powers on in the following state:
• The device is in low-power Shutdown mode,
requiring a low-to-high transition on SCIO to enter
Idle mode
• The Write Enable Latch (WEL) is reset
• The internal Address Pointer is undefined
• A low-to-high transition, standby pulse and
subsequent high-to-low transition on SCIO (the
first low pulse of the header) are required to enter
the active state
.
TABLE 6-1:
WEL
0
1
WRITE PROTECT FUNCTIONALITY MATRIX
Protected Blocks
Unprotected Blocks
Protected
Protected
Protected
Writable
Status Register
Protected
Writable
DS20002122D-page 16
2008-2016 Microchip Technology Inc.










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