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PDF ( 数据手册 , 数据表 ) 74LV138DB

零件编号 74LV138DB
描述 3-to-8 line decoder/demultiplexer
制造商 NXP Semiconductors
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74LV138DB 数据手册, 描述, 功能
74LV138
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 — 4 March 2016
Product data sheet
1. General description
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC138 and 74HCT138.
The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
active LOW outputs (Y0 to Y7).
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The
74LV138 can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C







74LV138DB pdf, 数据表
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
Table 8. Measurement points
Supply voltage
VCC
< 2.7 V
2.7 V to 3.6 V
4.5 V
Input
VM
0.5VCC
1.5 V
0.5VCC
Output
VM
0.5VCC
1.5 V
0.5VCC
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Fig 8.
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Test circuit for measuring switching times
Table 9. Test data
Supply voltage
VCC
< 2.7 V
2.7 V to 3.6 V
4.5 V
Input
VI
VCC
2.7 V
VCC
tr, tf
2.5 ns
2.5 ns
2.5 ns
74LV138
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 16







74LV138DB equivalent, schematic
NXP Semiconductors
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
74LV138
3-to-8 line decoder/demultiplexer; inverting
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 March 2016
Document identifier: 74LV138










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