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PDF ( 数据手册 , 数据表 ) WM8255

零件编号 WM8255
描述 Single Channel 16-bit CIS/CCD AFE
制造商 Wolfson
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WM8255 数据手册, 描述, 功能
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WM8255
Single Channel 16-bit CIS/CCD AFE with RGB LED Current Drive
DESCRIPTION
The WM8255 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12 MSPS.
The device includes a complete signal processing channel
containing Reset Level Clamping, Correlated Double
Sampling, Programmable Gain and Offset adjust functions.
Internal multiplexers allow fast switching of offset and gain
for line-by-line colour processing. The output from this
channel is time multiplexed into a high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in a 2 bit or 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
The device includes an RGB LED current drive using current
and PWM functionality to control the operation of sensor
LEDs.
The device typically uses an analogue supply voltage of
5.75V and a digital interface supply of 3.3V.
BLOCK DIAGRAM
FEATURES
16-bit ADC
12 MSPS conversion rate
Low power – 250 mW typical
5.75V and 3.3V supply operation
Single channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
RGB LED current drive using current and PWM
2-bit or 4-bit wide multiplexed data output format
Internally generated voltage references
28-lead QFN package
3 wire serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
WOLFSON MICROELECTRONICS plc
Production Data, August 2013, Rev 4.7
Copyright 2013 Wolfson Microelectronics plc







WM8255 pdf, 数据表
Production Data
WM8255
Test Conditions
AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN TYP MAX
Programmable Gain Amplifier
Resolution
Gain equation
8
0.78
PGA[7 : 0]
255
7.57
Max gain
Min gain
Internal channel offset
Analogue to Digital Converter
GMAX
GMIN
VOFF
8 8.35 8.7
0.72 0.78 0.82
10
Resolution
16
Maximum Speed
12
Full-scale input range
(2*(VRT-VRB))
VFS
2.0
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital Outputs
VIH
VIL
IIH
IIL
CI
0.7 DVDD
0.2 DVDD
1
1
5
High level output voltage
VOH
Low level output voltage
VOL
Supply Currents (LED Current DAC switched off)
Total supply current active
IOH = 1mA
IOL = 1mA
DVDD - 0.5
42.5
0.5
Total analogue AVDD, supply
current active
Total digital core, DVDD, supply
current active
Supply current full power down
mode
IAVDD
IDVDD1
39
3.5
500
Notes:
1. Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is
measured with approximately 50pF attached to the pin.
UNIT
bits
V/V
V/V
V/V
mV
bits
MSPS
V
V
V
A
A
pF
V
V
mA
mA
mA
A
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PD, Rev 4.7, August 2013
8







WM8255 equivalent, schematic
Production Data
WM8255
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (VFS = 2.0V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 10 represents the processing of the video signal through the WM8255.
INPUT
SAMPLING OFFSET DAC PGA
BLOCK
BLOCK BLOCK
V1 V2 V3
ADC BLOCK
+0
x (65535/VFS)
if PGAFS[1:0]=11
D1
OUTPUT
INVERT
BLOCK
D2
- XVIN + ++
analog
+65535 if PGAFS[1:0]=10
+32767 if PGAFS[1:0]=0x digital
OP pins
CDS = 1
VRESET
PGA gain
A= 0.78+PGA[7:0]x7.57/255
D2 = D1 if INVOP = 0
D2 = 65535-D1 if INVOP = 1
CDS = 0
VVRLC
VRLCEXT=1 VRLCEXT=0
Offset
DAC
250mV*(DAC[7:0]-127.5)/127.5
VIN is VINP
VRESET is VIN sampled during reset clamp
VRLC is voltage applied to VRLC/VBIAS pin
RLC See parametrics for
DAC DAC voltages.
CDS, VRLCEXT, RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
Figure 10 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally
set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8255.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the
input video.
V1 =
VIN - VRESET
Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V1 =
VIN - VVRLC
Eqn. 2
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.
VVRLC
=
(VRLCSTEP RLCV[3:0]) + VRLCBOT
Eqn. 3
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PD, Rev 4.7, August 2013
16










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