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PDF ( 数据手册 , 数据表 ) GD25Q32C

零件编号 GD25Q32C
描述 3.3V Uniform Sector Dual and Quad Serial Flash
制造商 ELM
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GD25Q32C 数据手册, 描述, 功能
http://www.elm-tech.com
GD25Q32C
DATASHEET







GD25Q32C pdf, 数据表
GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
5. DATA PROTECTION
http://www.elm-tech.com
The GD25Q32C provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the
memory array that can be read but not change.
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
Table1.0 GD25Q32C Protected area size (CMP=0)
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
××000
00001
00010
00011
00100
00101
00110
01001
01010
01011
01100
01101
01110
××111
10001
10010
10011
1010×
10110
11001
11010
11011
1110×
11110
Blocks
NONE
63
62 to 63
60 to 63
56 to 63
48 to 63
32 to 63
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
63
63
63
63
63
0
0
0
0
0
Addresses
NONE
3F0000H-3FFFFFH
3E0000H-3FFFFFH
3C0000H-3FFFFFH
380000H-3FFFFFH
300000H-3FFFFFH
200000H-3FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
3FF000H-3FFFFFH
3FE000H-3FFFFFH
3FC000H-3FFFFFH
3F8000H-3FFFFFH
3F8000H-3FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH
Density
NONE
64KB
128KB
256KB
512KB
1MB
2MB
64KB
128KB
256KB
512KB
1MB
2MB
4MB
4KB
8KB
16KB
32KB
32KB
4KB
8KB
16KB
32KB
32KB
Portion
NONE
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
50 - 8
Rev.1.0







GD25Q32C equivalent, schematic
GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Figure 4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
01234567
Command(50H)
SI
SO High-Z
7.4. Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to
the device. It is also possible to read the Status Register continuously. For command code “05H”“35H”“15H”,
the SO will output Status Register bits S7~S0 / S15~S8 / S16~S23.
Figure 5. Read Status Register Sequence Diagram
7.5. Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S23, S20, S19, S18, S17, S16, S15, S10, S1
and S0 of the Status Register. CS# must be driven high after the eighth of the data byte has been latched in.
If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-
timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write
In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When
the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register
50 - 16
Rev.1.0










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