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PDF ( 数据手册 , 数据表 ) SMB110

零件编号 SMB110
描述 Five Channel Programmable DC-DC System Power Manager
制造商 Summit
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SMB110 数据手册, 描述, 功能
Five Channel Programmable DC-DC System Power Manager
SMB110
Preliminary Information
FEATURES & APPLICATIONS
Digital programming of all major parameters via I2C
interface and non-volatile memory
o Output voltage set point
o Output power-up/down sequencing
o Input/Battery voltage monitoring
o Digital soft-start and output slew rate
o Output voltage margining
o UV/OV monitoring of all outputs
o Enable/Disable outputs independently
Five output channels
o Two synchronous step-down (buck) channels
o One step-up (boost) channel
o One inverting (buck-boost) channel
o One fixed output +3.3V LDO
User friendly Graphical User Interface (GUI)
+2.7V to +6.0V Input Range
Highly accurate reference and output voltage (<0.5%)
with Active DC Output Control (ADOC™) technology
Undervoltage Lockout (UVLO) with hysteresis
800 kHz operating frequency
96 bytes of user configurable nonvolatile memory
Applications
Digital camcorders/still cameras
Portable DVD/MP3/GPS
Camera/smart phones
TFT Displays/Monitors/TV’s
Mobile Computing/PDA’s
Consumer battery-operated equipment
SIMPLIFIED APPLICATIONS DRAWING
SMB110
INTRODUCTION
The SMB110 is a highly integrated and flexible five-channel
power manager designed for use in a wide range of portable
applications. The built-in digital programmability allows system
designers to custom tailor the device to suit almost any multi-
channel power supply application from digital camcorders to
mobile phones. Complete with a user friendly GUI, all
programmable settings including output voltages and
input/output voltage monitoring can be customized with ease.
The SMB110 integrates all the essential blocks required to
implement a complete five-channel power subsystem including
two synchronous step-down “buck” controllers, one step-up
“boost” controller, one inverting “buck-boost” controller and one
fixed output +3.3V LDO. Additionally sophisticated power
control/monitoring functions required by complex systems are
built-in. These include digitally programmable output voltage
set point, power-up/down sequencing, enable/disable,
margining and UV/OV/input/output monitoring on all channels.
The integration of features and built-in flexibility of the SMB110
allows the system designer to create a “platform solution” that
can be easily modified via software without major hardware
changes. Combined with the re-programmability of the
SMB110 this facilitates rapid design cycles and proliferation
from a base design to future generations of product.
The SMB110 is suited to battery-powered applications with an
input range of +2.7V to +6.0V. Output voltages are extremely
accurate (<0.5%) employing proprietary ADOC™ technology.
Communication is via the industry standard I2C bus. All user-
programmed settings are stored in non-volatile EEPROM of
which 96 bytes may be used for general-purpose memory
applications. The operating temperature range is +0C to +70C
and the available package is a lead-free, Green, RoHS
compliant, 32-pad QFN-32.
+2.7V to +6.0V
or
Li-Ion
LDO
Inverter
Channel
+3.3V @20mA
MCU/RTC
-0.8V to -30V (Prog.) @UP TO1A
CCD
I2C/SMBus
Reset Input
Reset Output
Power Good
System
Control and
Monitoring
Step-Up
(Boost)
Channels
2 Step-
Down
(Buck)
Channels
Vin to +30V (Prog.) @ UP TO 1A
TFT/LCD
+0.8V to 0.9 x Vin (Prog.) @ 2A
Memory, I/O
+0.8V to 0.9 x Vin (Prog.) @ 2A
CPU Core
Figure 1 – Applications diagram featuring the SMB110 five-channel, programmable DC-DC controller
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT Microelectronics, Inc. 2005
1717 Fox Drive • San Jose CA 95131 •
http://www.summitmicro.com/
2099 2.3 5/3/2005
Phone 408 436-9890 • FAX 408 436-9897
1







SMB110 pdf, 数据表
SMB110
Preliminary Information
PIN DESCRIPTION
Pin Number
Pin Type
27 OUT
28
29
30
31
32
PAD
IN
IN
IN
IN
PWR
PWR
Pin Name
HSDRV_CH3
PWREN0
COMP2_CH3
COMP1_CH3
VM_CH3
GND
GND
Pin Description
The HSDRV_CH3 (Channel 3 High-side Driver) pin is the upper
switching node of the channel 3 synchronous buck controller. Attach
to the gate of p-channel MOSFET. A delay exists between the
assertion of HSDRV_CH3 and assertion of LSDRV_CH3 to prevent
excessive current flow during switching.
The PWREN0 (Power Enable 0) pin is a programmable input used to
enable (disable) selected supplies. When unused this pin should be
tied to a solid logic level.
The COMP2_CH3 (Channel 3 secondary Compensation) pin is the
secondary compensation input of the channel 3 buck controller.
The COMP1_CH3 (Channel 3 primary Compensation) pin is the
primary compensation input of the channel 3 buck controller. Each
pin is internally connected to a programmable resistor divider.
The VM_CH3 (Channel 3 Voltage Monitor) pin connects the channel
3 controller output. Internally the VM_CH3 pin connects to an internal
programmable resistor divider.
The GND pin should be connected to the common ground plane
through a short fat wire.
The exposed metal pad should be attached to ground.
Summit Microelectronics, Inc
2099 2.3 3/1/2005
8







SMB110 equivalent, schematic
SMB110
Preliminary Information
I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS –100 kHz
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Description
Conditions
100kHz
Min Typ Max Units
fSCL
TLOW
THIGH
tBUF
tSU:STA
tHD:STA
tSU:STO
tAA
tDH
tR
tF
tSU:DAT
tHD:DAT
TI
SCL clock frequency
Clock low period
Clock high period
Bus free time
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to data valid
Data output hold time
SCL and SDA rise time
SCL and SDA fall time
Data in setup time
Data in hold time
Noise filter SCL and SDA
Before new transmission - Note
1/
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA
change
Note 1/
Note 1/
Noise suppression
0
4.7
4.0
4.7
4.7
4.0
4.7
0.2
0.2
250
0
100 kHz
µs
µs
µs
µs
µs
µs
3.5 µs
µs
1000 ns
300 ns
ns
ns
100 ns
tWR_CONFIG
tWR_EE
Write cycle time config
Write cycle time EE
Configuration registers
Memory array
10 ms
5 ms
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tR
TIMSICNLG DIAGRAMS
tSU:SDA
SDA (IN)
SDA (OUT)
tAA
tF
tHD:SDA
Figure 4 – I2C timing diagram
tHIGH
tHD:DAT
tLOW
tSU:DAT
tDH
tSU:STO
tWR (For Write Operation Only)
tBUF
Summit Microelectronics, Inc
2099 2.3 3/1/2005
16










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