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PDF ( 数据手册 , 数据表 ) IS43TR81280BL

零件编号 IS43TR81280BL
描述 1Gb DDR3 SDRAM
制造商 ISSI
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IS43TR81280BL 数据手册, 描述, 功能
IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
128MX8, 64MX16 1Gb DDR3 SDRAM
FEATURES
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
High speed data transfer rates with system
frequency up to 1066 MHz
8 internal banks for concurrent operation
8n-bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
OPTIONS
Configuration:
128Mx8
64Mx16
Package:
96-ball FBGA (9mm x 13mm) for x16
78-ball FBGA (8mm x 10.5mm) for x8
NOVEMBER 2014
Refresh Interval:
7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
Write Leveling
Operating temperature:
Commercial (TC = 0°C to +95°C)
Industrial (TC = -40°C to +95°C)
Automotive, A1 (TC = -40°C to +95°C)
Automotive, A2 (TC = -40°C to +105°C)
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Page size
Auto Precharge Addressing
BL switch on the fly
128Mx8
A0-A13
A0-A9
BA0-2
1KB
A10/AP
A12/BC#
64Mx16
A0-A12
A0-A9
BA0-2
2KB
A10/AP
A12/BC#
SPEED BIN
Speed Option
15G
125J
107M
093N
JEDEC Speed Grade
DDR3-1333G DDR3-1600J DDR3-1866M DDR3-2133N
CL-nRCD-nRP
8-8-8
10-10-10
13-13-13
14-14-14
tRCD,tRP(min)
12.0
12.5
13.91
13.09
Note: Faster speed options may be backward compatible to slower speed options. Refer to timing tables (8.3)
Units
tCK
ns
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. www.issi.com
Rev. C1
11/12/2014
1







IS43TR81280BL pdf, 数据表
IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
2.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET
needs to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being de-asserted (min. time 10
ns).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta Tb Tc
Td
Te Tf Tg Th
Ti
Tj
Tk
(( (( (( (( (( (( (( (( ((
CK,CK# )( )( )( )( )( )( )( )( )( )( )( )( )( )( )( )( )( )(
)) )) )) )) )) )) )) )) ))
VDD,VDDQ
((
))
tCKSRX
((
))
((
))
(( ((
)) ))
((
))
(( (( ((
)) )) ))
RESET#
CKE
T=100nS
((
))
Tmin=10nS
((
)( )(
))
T=5(0(0µS
))
tIS
((
))
((
)( )(
))
(( ((
)) ))
((
))
(( (( ((
)( )( )( )( )( )(
)) )) ))
(( ((
)) ))
(( ((
)( )( )( )(
)) ))
tDLLK
((
))
((
)( )( Valid
))
CMMAND
BA
ODT
((
)( )(
))
((
)( )(
))
((
)( )(
))
tXPR
tIS
tMRD
tMRD
tMRD
tMOD
tZQinit
(( (( (( (( (( (( (( ((
)( )(
1) )( )( MRD )( )( MRD )( )( MRD )( )( MRD )( )( ZQCL )( )(
1) )( )( Valid
)) )) )) )) )) )) )) ))
((
(( (( (( ((
(( (( ((
)( )( )( )( MR2 )( )( MR3 )( )( MR1 )( )( MR0 )( )( )( )( )( )( Valid
))
)) )) )) ))
)) )) ))
tIS tIS
(( ((
(( ((
)( )( Stat)(i)(c LOW in case RTT_Nom is enabled at time Tg, otherwise static HIG)( H)( or LOW )( )( Valid
)) ))
)) ))
RTT
((
((
((
(( ((
((
(( ((
))
))
))
)) ))
))
)) ))
Note1. From time point Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
( ( Time
))
Break
Figure2.1.2 Reset Procedure at Power Stable Condition
((
))
DON’T
CARE
2.3 Register Definition
2.3.1 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by
the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command.
As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized
and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers
can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even
if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must
be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which
means these commands can be executed any time after power-up without affecting the array contents The mode register
set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time
required between two MRS commands shown as below.
Integrated Silicon Solution, Inc. www.issi.com
Rev. C1
11/12/2014
8







IS43TR81280BL equivalent, schematic
IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
Memory Core
(all banks
precharged)
MR3[A2]
Multipurpose
Register pre-defined
data for read
DQ, DM, DQS, DQS#
Figure 2.3.5.1 MPR Block Diagram
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1. Prior to
issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is
enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register.
The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled.
When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the
MPR disabled (MR3 bit A2 = 0).
Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of
RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR
enable mode. The RESET function is supported during MPR enable mode.
MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
MPR
MPR-Loc
0b don’t care (0b or 1b)
1b See MPR Definition
table
Function
Normal operation, no MPR transaction. All subsequent Reads will come from DRAM
array. All subsequent Write will go to DRAM array.
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
Integrated Silicon Solution, Inc. www.issi.com
Rev. C1
11/12/2014
16










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