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PDF ( 数据手册 , 数据表 ) IS46DR32801B

零件编号 IS46DR32801B
描述 8Mx32 256Mb DDR2 DRAM
制造商 ISSI
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IS46DR32801B 数据手册, 描述, 功能
IS43/46DR32801B
8Mx32
256Mb DDR2 DRAM
FEATURES
• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers
per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions
with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6
supported
• Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, and 5 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and
reduced strength options
• On-die termination (ODT)
OPTIONS
• Configuration:
8M x 32 (IS43/46DR32801B - 8K refresh)
• Package: x32: 126-ball WBGA
• Timing – Cycle time
2.5ns @CL=6, DDR2-800E
3.0ns @CL=5, DDR2-667D
3.75ns @CL=4, DDR2-533C
5.0ns @CL=3, DDR2-400B
• Temperature Range:
Commercial (0°C Tc 85°C; 0°C Ta 70°C)
Industrial (–40°C Tc 95°C; –40°C Ta 85°C)
Automotive, A1 (–40°C Tc 95°C; –40°C Ta 85°C)
Automotive, A2 (–40°C Tc 105°C; –40°C Ta 105°C)
Tc = Case Temp, Ta = Ambient Temp
ADVANCED INFORMATION
JUNE 2012
DESCRIPTION
ISSI's 256Mb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
The 256Mb DDR2 SDRAM is provided in a wide bus
x32 format, designed to offer a smaller footprint and
support compact designs.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
Row Addressing
Column
Addressing
Bank Addressing
Precharge
Addressing
8M x 32
4M x 32 x 4 banks
8K/64ms
A0-A12
A0-A7
BA0, BA1
A10/AP
KEY TIMING PARAMETERS
Speed Grade -25E -3D -37C
tRCD
15 15 15
tRP 15 15 15
tRC 60 60 60
tRAS
45 45 45
tCK @CL=3
555
tCK @CL=4
3.75 3.75 3.75
tCK @CL=5
3 3 3.75
tCK @CL=6
2.5 3 3.75
-5B
15
15
55
40
5
5
5
5
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
06/07/2012
1







IS46DR32801B pdf, 数据表
IS43/46DR32801B
Input DC logic level
Symbol Parameter
VIH(dc)
VIL(dc)
dc input logic HIGH
dc input logic LOW
Min.
VREF + 0.125
- 0.3
Max.
VDDQ + 0.3
VREF - 0.125
Units
V
V
Notes
Input AC logic level
Symbol Parameter
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Units Notes
Min.
Max.
Min.
Max
VIH (ac) ac input logic HIGH VREF + 0.250 VDDQ + Vpeak VREF + 0.200 VDDQ + Vpeak V 1
VIL (ac) ac input logic LOW VSSQ - Vpeak VREF - 0.250 VSSQ - Vpeak VREF - 0.200 V 1
Notes:
1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
AC Input Test Conditions
Symbol
Condition
Value
Units Notes
VREF
Input reference voltage
0.5 x VDDQ
V1
VSWING(MAX) Input signal maximum peak to peak swing
1.0
V1
SLEW
Input signal minimum slew rate
1.0 V/ns 2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to
VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the
negative transitions.
AC input test signal waveform
VSWING(MAX)
Falling Slew =
DTF
VREF - VIL(ac) max
DTF
8
DTR
Rising Slew =
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
VIH(ac) min - VREF
DTR
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
06/07/2012







IS46DR32801B equivalent, schematic
IS43/46DR32801B
Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)
(For information related to the entries in this table, refer to both the Guidelines and the Specific Notes following this Table.)
Parameter
Clock cycle time, CL=x
CK HIGH pulse width
Symbol
tCK
tCH
DDR2-400
Min. Max.
58
0.45 0.55
DDR2-533
Min. Max
3.75 8
0.45 0.55
Units Notes
ns 15
tCK
CK LOW pulse width
tCL 0.45 0.55 0.45 0.55 tCK
DQS latching rising transitions to associated clock edges tDQSS
- 0.25
0.25
- 0.25
0.25 tCK
DQS falling edge to CK setup time
tDSS
0.2
0.2 – tCK
DQS falling edge hold time from CK
tDSH
0.2
0.2 – tCK
DQS input HIGH pulse width
tDQSH
0.35
0.35 – tCK
DQS input LOW pulse width
tDQSL
0.35
0.35 – tCK
Write preamble
tWPRE
0.35
0.35 – tCK
Write postamble
Address and control input setup time
Address and control input hold time
Address and control input setup time
Address and control input hold time
Control & Address input pulse width for each input
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (differential strobe)
tWPST
0.4
0.6
0.4 0.6 tCK 10
tISa
600
500
ps
5, 7, 9, 22,
29
tIHa
600
500
ps
5, 7, 9, 23,
29
tIS(base)
350
250
ps
5, 7, 9, 22,
29
tIH(base)
475
375
ps
5, 7, 9, 23,
29
tIPW
0.6
0.6 – tCK
tDSa
400
350 – ps 6, 7, 8, 20,
28, 31
tDHa
400
350
ps
6, 7, 8, 21,
28, 31
tDS(base)
150
100
ps
6, 7, 8, 20,
28, 31
tDH(base)
275
225
ps
6, 7, 8, 21,
28, 31
DQ and DM input setup time (single-ended strobe)
tDS1(base)
25
– - 25 – ps 6, 7, 8, 25
DQ and DM input hold time (single-ended strobe)
tDH1(base)
25
– - 25 – ps 6, 7, 8, 26
DQ and DM input pulse width for each input
DQ output access time from CK/CK
DQS output access time from CK/ CK
Data-out high-impedance time from CK/ CK
DQS(DQS) low-impedance time from CK/ CK
DQ low-impedance time from CK/ CK
tDIPW
0.35
0.35 – tCK
tAC
- 600
+ 600
- 500
+ 500
ps
tDQSCK
- 500
+ 500
- 450
+ 450
ps
tHZ tAC max tAC max ps 18
tLZ(DQS) tAC min tAC max tAC min tAC max ps 18
tLZ(DQ) 2 x tAC min tAC max 2 x tAC min tAC max ps 18
DQS-DQ skew for DQS and associated DQ signals
CK half pulse width
tDQSQ
tHP
min (tCL,
tCH)
350
min (tCL,
tCH)
300
ps 13
ps 11,12
DQ hold skew factor
DQ/DQS output hold time from DQS
tQHS
tQH
– 450 – 400
tHP - tQHS – tHP - tQHS –
ps 12
ps
Read preamble
Read postamble
tRPRE 0.9 1.1 0.9 1.1 tCK 19
tRPST 0.4 0.6 0.4 0.6 tCK 19
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
06/07/2012










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