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PDF ( 数据手册 , 数据表 ) IS42VM16160E

零件编号 IS42VM16160E
描述 4M x 16Bits x 4Banks Mobile Synchronous DRAM
制造商 ISSI
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IS42VM16160E 数据手册, 描述, 功能
IS42/45SM/RM/VM16160E
4M x 16Bits x 4Banks Mobile Synchronous DRAM
Description
These IS42/45SM/RM/VM16160E are mobile 268,435,456 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 16
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply.
Auto refresh and self refresh.
All pins are compatible with LVCMOS interface.
8K refresh cycle / 64ms.
Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
Programmable CAS Latency : 2,3 clocks.
All inputs and outputs referenced to the positive edge of the
system clock.
Data mask function by DQM.
Internal 4 banks operation.
Burst Read Single Write operation.
Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
- Programmable Driver Strength Control
Full Strength or 3/4, 1/2, 1/4, 1/8 of Full Strength
- Deep Power Down Mode
Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. 0C | May 2013
www.issi.com - [email protected]
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IS42VM16160E pdf, 数据表
IS42/45SM/RM/VM16160E
Functional Description
In general, this 256Mb SDRAM (4M x 16Bits x 4banks) is a multi-bank DRAM that operates at 3.3V/2.5V/1.8V and includes a
synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is
organized as 8,192 rows by 512 columns by 16-bits
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and
row to be accessed (BA0-BA1 select the bank, A0-A12 select the row). The address bits (BA0-BA1 select the bank, A0-A8 select the
column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in
undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a
signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the PRECHARGE command
has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is
ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to
applying any operational command. And a extended mode register set command will be issued to program specific mode of self
refresh operation(PASR). The following these cycles, the Mobile SDRAM is ready for normal operation.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst
length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10-M12 should be set to zero. M13 and M14
should be set to zero to prevent extended mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will result in unspecified operation.
Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are
special features of the BATRAM device. They include Partial Array Self Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command and retains the stored information until it is
programmed again or the device loses power.
The Extended Mode Register must be programmed with E8 through E12 set to 0. Also, E13 (BA0) must be set to 0”, and E14 (BA1)
must be set to 1. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in
unspecified operation.
Rev. 0C | May 2013
www.issi.com - [email protected]
8







IS42VM16160E equivalent, schematic
IS42/45SM/RM/VM16160E
Note :
1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA.
Rev. 0C | May 2013
www.issi.com - [email protected]
16










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