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PDF ( 数据手册 , 数据表 ) IS42VS16100F

零件编号 IS42VS16100F
描述 512K Words x 16 Bits x 2 Banks 16Mb SDRAM
制造商 ISSI
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IS42VS16100F 数据手册, 描述, 功能
IS42/45S16100F, IS42VS16100F
512K Words x 16 Bits x 2 Banks
16Mb SDRAM
JUNE 2012
FEATURES
• Clock frequency:
IS42/45S16100F: 200, 166, 143 MHz
IS42VS16100F: 133, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single power supply:
IS42/45S16100F: Vdd/Vddq = 3.3V
IS42VS16100F: Vdd/Vddq = 1.8V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Packages 400-mil 50-pin TSOP-II and 60-ball
BGA
• Lead-free package option
• Available in Industrial Temperature
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100F,
IS45S16100F and IS42VS16100F are each organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-
speed data transfer using pipeline architecture. All
inputs and outputs signals refer to the rising edge of the
clock input.
ADDRESS TABLE
Parameter
Power Supply Vdd/Vddq
Refresh Count
Row Addressing
IS42/45S16100F IS42VS16100F
3.3V
1.8V
2K/32ms
2K/32ms
A0-A10
Column Addressing
Bank Addressing
Precharge Addressing
A0-A7
A11
A10
KEY TIMING PARAMETERS
Parameter
CLK Cycle Time
-5(1) -6(2) -7 (2) -75 (3) -10 (3) Unit
CAS Latency = 3 5 6 7 7.5 10 ns
CAS Latency = 2 10 10 10 10 12 ns
CLK Frequency
CAS Latency = 3 200 166 143 133 100 Mhz
CAS Latency = 2 100 100 100 100 83 Mhz
Access Time from
Clock
CAS Latency = 3
5 5.5 5.5 6
7 ns
CAS Latency = 2 6 6 6 8 8 ns
Notes:
1. Available for IS42S16100F only
2. Available for IS42S16100F and IS45S16100F only
3. Available for IS42VS16100F only
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
06/13/2012
1







IS42VS16100F pdf, 数据表
IS42/45S16100F, IS42VS16100F
IS42S16100F and IS45S16100F AC CHARACTERISTICS(1,2,3)
-5
Symbol Parameter
Min. Max.
tck3
tck2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
5 —
10 —
tac3
tac2
Access Time From CLK(4)
CAS Latency = 3
CAS Latency = 2
— 5
— 6
tchi
CLK HIGH Level Width
2 —
tcl CLK LOW Level Width
2 —
toh3
toh2
Output Data Hold Time
CAS Latency = 3
CAS Latency = 2
2 —
2.5 —
tlz Output LOW Impedance Time
0 —
thz3
thz2
Output HIGH Impedance Time(5)
CAS Latency = 3
CAS Latency = 2
— 5
— 6
tds Input Data Setup Time
2 —
tdh Input Data Hold Time
1 —
tas Address Setup Time
2 —
tah Address Hold Time
1 —
tcks CKE Setup Time
2 —
tckh CKE Hold Time
1 —
tcka CKE to CLK Recovery Delay Time
1CLK+3 —
tcs Command Setup Time (CS, RAS, CAS, WE, DQM)
2 —
tch Command Hold Time (CS, RAS, CAS, WE, DQM)
1 —
trc Command Period (REF to REF / ACT to ACT)
50 —
tras Command Period (ACT to PRE)
35 100,000
trp Command Period (PRE to ACT)
15 —
trcd Active Command To Read / Write Command Delay Time 15 —
trrd Command Period (ACT [0] to ACT[1])
10 —
tdpl3
tdpl2
Input Data To Precharge
Command Delay time
CAS Latency = 3
CAS Latency = 2
2CLK —
2CLK —
tdal3
tdal2
Input Data To Active / Refresh
CAS Latency = 3 2CLK+trp
Command Delay time (During Auto-Precharge) CAS Latency = 2 2CLK+trp
-6 -7
Min. Max. Min. Max. Units
6 —
10 —
7 —
10 —
ns
ns
— 5.5
— 6
— 5.5
— 6
ns
ns
2.5 —
2.5 — ns
2.5 —
2.5 — ns
2.0 —
2.5 —
2.0 —
2.5 —
ns
ns
0 —
0 — ns
— 5.5
— 6
— 5.5
— 6
ns
ns
2 —
2 — ns
1 —
1 — ns
2 —
2 — ns
1 —
1 — ns
2 —
2 — ns
1 —
1 — ns
1CLK+3 — 1CLK+3 — ns
2 —
2 — ns
1 —
1 — ns
54 —
63 — ns
36 100,000 42 100,000 ns
18 —
20 — ns
18 —
20 — ns
12 —
14 — ns
2CLK —
2CLK —
2CLK —
2CLK —
ns
ns
2CLK+trp
2CLK+trp
2CLK+trp
2CLK+trp
ns
ns
txsr Exit Self-Refresh to Active Time
55 —
60 —
70 —
tt Transition Time
0.3 1.2
0.3 1.2
0.3 1.2
tref Refresh Cycle Time (2048)
— 32
— 32
— 32
Notes:
1. When power is first applied, memory operation should be started 100 µs after Vdd and Vddq reach their stipulated voltages. Also note that the power-on
sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns. If clock rising time is longer than 1ns, (tt/2 - 0.5)ns should be added to the parameter.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between Vih (min.) and Vil (max.).
4. Access time is measured at 1.4V with the load shown in the figure that follows.
5. The time thz (max.) is defined as the time required for the output voltage to transition by ± 200 mV from Voh (min.) or Vol (max.) when the
output is in the high impedance state.
ns
ns
ms
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
06/13/2012







IS42VS16100F equivalent, schematic
IS42/45S16100F, IS42VS16100F
COMMANDS (cont.)
Self-Refresh Command
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
Clock Suspend Command
CLK
CKE BANK(S) ACTIVE
CS
RAS
CAS
WE
A0-A9
A10
A11
NOP
NOP
NOP
NOP
Power Down Command
CLK
CKE ALL BANKS IDLE
CS
RAS
CAS
WE
A0-A9
A10
A11
NOP
NOP
NOP
NOP
Burst Stop Command
CLK
CKE HIGH
CS
RAS
CAS
WE
A0-A9
A10
A11
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
06/13/2012










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