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PDF ( 数据手册 , 数据表 ) H8S2390

零件编号 H8S2390
描述 16-Bit Single-chip Microcomputer
制造商 Hitachi
LOGO Hitachi LOGO 


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H8S2390 数据手册, 描述, 功能
Hitachi 16-Bit Single-chip Microcomputer
H8S/2357 Series,
H8S/2357
H8S/2352
H8S/2390
H8S/2392
H8S/2394
H8S/2398
ADE-602-146C
Rev. 4.0
09/05/01
Hitachi, Ltd.
H8S/2357F-ZTATTM
H8S/2398F-ZTATTM
H8S/2396F-ZTATTM
H8S/2395F-ZTATTM
Hardware Manual







H8S2390 pdf, 数据表
Section
Item
Revisions (See Manual for Details)
10.4.5
Cascaded
Operation
Figure 10-23 Example of Description amended from "TCLKA" to "TCLKC" and
Cascaded Operation (2) from "TCLKB" to "TCLKD"
13.2.3 Reset Bit 5–Reset Select (RSTS)
Control/Status
Register
(RSTCSR)
Note amended
14.2.7 Serial 14.2.7 Serial Status
Status
Register (SSR)
Register (SSR)
Description amended
18.3 Operation 18.3 Operation
Note added
19.1 Overview 19.1 Overview
Description amended
19.2.2 Bus
Control
Register L
(BCRL)
Bit 5–External Address
Enable (EAE)
Notes added
19.3 Operation Table 19-3 Operating
Modes and ROM Area
Notes added
19.13.3
Programmer
Mode
Operation
Table 19-19 Setting for
Each Operating Mode in
Programmer Mode
Pin names modified
19.13.5 Auto- Figure 19-29 Auto-Program Pin names modified
Program Mode Mode Timing Waveforms
Notes on Use of Auto-
Program Mode
Modified
19.13.6 Auto- Figure 19-30 Auto-Erase Pin names modified
Erase Mode Mode Timing Waveforms
Notes on Use of Auto-
Erase Mode
Modified
19.13.7 Status Figure 19-31 Status Read Pin names modified
Read Mode Mode Timing Waveforms
Table 19-27 Status Read Pin names and note modified
Mode Return Commands







H8S2390 equivalent, schematic
4.2.3 Reset Sequence..................................................................................................... 95
4.2.4 Interrupts after Reset ............................................................................................ 96
4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. 96
4.3 Traces ................................................................................................................................ 97
4.4 Interrupts............................................................................................................................ 97
4.5 Trap Instruction ................................................................................................................. 98
4.6 Stack Status after Exception Handling .............................................................................. 99
4.7 Notes on Use of the Stack.................................................................................................. 99
Section 5 Interrupt Controller ............................................................................101
5.1 Overview............................................................................................................................ 101
5.1.1 Features ................................................................................................................ 101
5.1.2 Block Diagram...................................................................................................... 102
5.1.3 Pin Configuration ................................................................................................. 103
5.1.4 Register Configuration ......................................................................................... 103
5.2 Register Descriptions......................................................................................................... 104
5.2.1 System Control Register (SYSCR) ...................................................................... 104
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 105
5.2.3 IRQ Enable Register (IER) .................................................................................. 106
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 107
5.2.5 IRQ Status Register (ISR) .................................................................................... 108
5.3 Interrupt Sources................................................................................................................ 109
5.3.1 External Interrupts................................................................................................ 109
5.3.2 Internal Interrupts ................................................................................................. 110
5.3.3 Interrupt Exception Handling Vector Table ......................................................... 110
5.4 Interrupt Operation ............................................................................................................ 114
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 114
5.4.2 Interrupt Control Mode 0...................................................................................... 117
5.4.3 Interrupt Control Mode 2...................................................................................... 119
5.4.4 Interrupt Exception Handling Sequence .............................................................. 121
5.4.5 Interrupt Response Times..................................................................................... 123
5.5 Usage Notes ....................................................................................................................... 124
5.5.1 Contention between Interrupt Generation and Disabling..................................... 124
5.5.2 Instructions that Disable Interrupts ...................................................................... 125
5.5.3 Times when Interrupts are Disabled..................................................................... 125
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 125
5.6 DTC and DMAC Activation by Interrupt.......................................................................... 126
5.6.1 Overview .............................................................................................................. 126
5.6.2 Block Diagram...................................................................................................... 126
5.6.3 Operation .............................................................................................................. 127
Section 6 Bus Controller....................................................................................129
6.1 Overview............................................................................................................................ 129
iii










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