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PDF ( 数据手册 , 数据表 ) COM20020IP3V

零件编号 COM20020IP3V
描述 COM20020 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM
制造商 SMSC Corporation
LOGO SMSC Corporation LOGO 


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COM20020IP3V 数据手册, 描述, 功能
COM20020 3.3V
COM20020 3.3V ULANC
Universal Local Area Network Controller
with 2K x 8 On-Board RAM
FEATURES
!" New Features
- Data Rates up to 5 Mbps
- Programmable Reconfiguration Times
!" 24 Pin DIP, 28 Pin PLCC Package
!" Ideal for Industrial/Factory/Building
Automation and Transportation
Applications
!" Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
!" Minimal Microcontroller and Media
Interface Logic Required
!" Flexible Interface For Use With All
Microcontrollers or Microprocessors
!" Automatically Detects Type of
Microcontroller Interface
!" 2Kx8 On-Chip Dual Port RAM
!" Command Chaining for Packet Queuing
!" Sequential Access to Internal RAM
!" Software Programmable Node ID
!" Eight, 256 Byte Pages Allow Four Pages TX
and RX Plus Scratch-Pad Memory
!" Next ID Readable
!" Internal Clock Scaler and Clock Multiplier for
Adjusting Network Speed
!" Operating Temperature Range of -40oC to
+85oC
!" Self-Reconfiguration Protocol
!" Supports up to 255 Nodes
!" Supports Various Network Topologies (Star,
Tree, Bus...)
!" CMOS, Single +3.3V Supply
!" Duplicate Node ID Detection
!" Powerful Diagnostics
!" Receive All Packets Mode
!" Flexible Media Interface:
- Traditional Hybrid Interface For Long
Distances up to Four Miles at 2.5Mbps.
- RS485 Differential Driver Interface For
Low Cost, Low Power, High Reliability
ORDERING INFORMATION
Order Numbers:
COM20020ILJP3V
28 PLCC Package
COM20020IP3V
24 DIP Package







COM20020IP3V pdf, 数据表
PROTOCOL DESCRIPTION
NETWORK PROTOCOL
Communication on the network is based on a
token passing protocol. Establishment of the
network configuration and management of the
network protocol are handled entirely by the
COM20020's internal microcoded sequencer. A
processor or intelligent peripheral transmits data
by simply loading a data packet and its destination
ID into the COM20020's internal RAM buffer, and
issuing a command to enable the transmitter.
When the COM20020 next receives the token, it
verifies that the receiving node is ready by first
transmitting a FREE BUFFER ENQUIRY
message. If the receiving node transmits an
ACKnowledge message, the data packet is
transmitted followed by a 16-bit CRC. If the
receiving node cannot accept the packet (typically
its receiver is inhibited), it transmits a Negative
AcKnowledge message and the transmitter
passes the token. Once it has been established
that the receiving node can accept the packet and
transmission is complete, the receiving node
verifies the packet. If the packet is received
successfully, the receiving node transmits an
ACKnowledge
message (or nothing if it is not received
successfully) allowing the transmitter to set the
appropriate status bits to indicate successful or
unsuccessful delivery of the packet. An interrupt
mask permits the COM20020 to generate an
interrupt to the processor when selected status
bits become true. Figure 1 is a flow chart
illustrating the internal operation of the
COM20020 connected to a 20 MHz crystal
oscillator.
DATA RATES
The COM20020 is capable of supporting data
rates from 156.25 Kbps to 5 Mbps. The following
protocol description assumes a 5 Mbps data rate.
To attain the faster data rates, the clock frequency
may be doubled by the internal clock multiplier
(see next section). For slower data rates, an
internal clock divider scales down the clock
frequency. Thus all timeout values are scaled as
shown in the following table:
Example: IDLE LINE Timeout @ 5 Mbps = 41 "s.
IDLE LINE Timeout for 156.2 Kbps is 41 "s * 32 =
1.3 ms
INTERNAL
CLOCK
FREQUENCY
40 MHz
20 MHz
CLOCK
PRESCALER
Div. by 8
Div. by 8
Div. by 16
Div. by 32
Div. by 64
Div. by 128
DATA RATE
5 Mbps
2.5 Mbps
1.25 Mbps
625 Kbps
312.5 Kbps
156.25 Kbps
TIMEOUT SCALING
FACTOR (MULTIPLY BY)
1
2
4
8
16
32
8







COM20020IP3V equivalent, schematic
High Speed CPU Bus Timing Support
High speed CPU bus support was added to the
COM20020. The reasoning behind this is as
follows: With the Host interface in Non-
multiplexed Bus mode, I/O address and Chip
Select signals must be stable before the read
signal is active and remain after the read signal
is inactive. But the High Speed CPU bus timing
doesn't adhere to these timings. For example, a
RISC type single chip microcontroller (like the
HITACHI SuperH series) changes I/O address at
the same time as the read signal. Therefore,
several external logic ICs would be required to
connect to this microcontroller.
In addition, the Diagnostic Status (DIAG) register
is cleared automatically by reading itself. The
internal DIAG register read signal is generated
by decoding the Address (A2-A0), Chip Select
(nCS) and Read (nRD) signals. The decoder will
A2-A0, nCS
generate a noise spike at the above tight timing.
The DIAG register is cleared by the spike signal
without reading itself. This is unexpected
operation. Reading the internal RAM and Next
Id Register have the same mechanism as
reading the DIAG register.
Therefore, the address decode and host
interface mode blocks were modified to fit the
above CPU interface to support high speed CPU
bus timing. In Intel CPU mode (nRD, nWR
mode), 3 bit I/O address (A2-A0) and Chip Select
(nCS) are sampled internally by Flip-Flops on the
falling edge of the internal delayed nRD signal.
The internal real read signal is the more delayed
nRD signal. But the rising edge of nRD doesn't
delay. By this modification, the internal real
address and Chip Select are stable while the
internal real read signal is active. Refer to figure
4 below.
VALID
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS
More delayed nRD
(nRD2)
VALID
FIGURE 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE
The I/O address and Chip Select signals, which Diagnostic register and generates the starting
are supplied to the data output logic, are not pulse of the RAM Arbitration. Typical delay time
sampled. Also, the nRD signal is not delayed, between nRD and nRD1 is around 15nS and
because the above sampling and delaying paths between nRD1 and nRD2 is around 10nS.
decrease the data access time of the read cycle.
Longer pulse widths are needed due to these
The above sampling and delaying signals are delays on nRD signal. However, the CPU can
supplied to the Read Pulse Generation logic insert some wait cycles to extend the width
which generates the clearing pulse for the without any impact on performance.
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