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PDF ( 数据手册 , 数据表 ) ADM1260

零件编号 ADM1260
描述 Super Sequencer
制造商 Analog Devices
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ADM1260 数据手册, 描述, 功能
Data Sheet
Super Sequencer with Interchip Bus and
Nonvolatile Fault Recording
ADM1260
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies per device
Interchip bus (ICB) simplifies multidevice connections and
sequencing system operation
Supports up to 4 devices
16 event deep black box nonvolatile fault recording
10 supply fault detectors enable supervision of supplies
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies
14.4 V on VH and 6.0 V on VP1 to VP4 (VPx)
5 dual function inputs: VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs: PDO1 to PDO10 (PDOx)
Open-collector with an external pull-up resistor
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
the PDOx outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in the SE
Program software control of sequencing through the SMBus
Complete voltage margining solution for 6 voltage rails
6 output voltage 8-bit DACs (0.300 V to 1.552 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Reference input (REFIN) with two input options
Driven directly from the 2.048 V (±0.25%) REFOUT pin
External reference for improved ADC performance
Powered by the highest voltage on either VPx or VH
Voltage on VPx or VH must be greater than the
undervoltage lockout (UVLO) threshold
Electronically erasable programmable read-only memory
(EEPROM)
Industry-standard, 2-wire bus interface (SMBus)
PDOx pins guaranteed low with VH and VPx = 1.2 V
Available in a 40-lead, 6 mm × 6 mm LFCSP package
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND
REFIN CDA
CCL SDA SCL A1 A0
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VREF
ADM1260
INTERCHIP
BUS
12-BIT
SAR ADC
CLOSED-LOOP
MARGINING SYSTEM
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
VOUT VOUT VOUT VOUT VOUT VOUT
DAC DAC DAC DAC DAC DAC
SMBus
INTERFACE
EEPROM
FAULT
RECORDING
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCAP
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
Figure 1.
VCCP GND
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
Digital signal processor (DSP)/field programmable gate
array (FPGA) supply sequencing
In-circuit testing of margined supplies
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADM1260 pdf, 数据表
ADM1260
Data Sheet
Parameter
SEQUENCING ENGINE TIMING
State Change Time
Black Box (Exit)
Min Typ Max Unit Test Conditions/Comments
45 μs
350 μs With delay or timeout configured as 0 μs in the state
1 At least one of the VH and VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Guaranteed by design.
Rev. 0 | Page 8 of 71







ADM1260 equivalent, schematic
ADM1260
INPUTS
SUPPLY SUPERVISION
The ADM1260 has 10 programmable inputs. Five of these inputs
are dedicated supply fault detectors (SFDs). These dedicated inputs
are VH and VPx (VP1 to VP4) by default. The other five inputs
are VXx (VX1 to VX5) and have dual functionality. These dual
function inputs can be used either as SFDs, with functionality
similar to that of VH and VPx, or as CMOS-/TTL-compatible
logic inputs to the device. Therefore, the ADM1260 can have up
to 10 analog inputs, a minimum of five analog inputs and five
digital inputs, or a combination thereof. If an input is used as an
analog input, it cannot be used as a digital input. Therefore, a
configuration requiring 10 analog inputs has no available digital
inputs. Table 6 shows the details of each input.
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1260 can have up to 10 SFDs on its 10 input channels.
These highly programmable reset generators enable the supervision
of up to 10 supply voltages. The supplies can be as low as 0.573 V
and as high as 14.4 V. The inputs can be configured to detect an
undervoltage fault (the input voltage drops below a preprogram-
med value), an overvoltage fault (the input voltage rises above a
preprogrammed value), or an out of window fault (the input
voltage is outside a preprogrammed range). The thresholds can
be programmed to an 8-bit resolution in registers provided in the
ADM1260. This 8-bit resolution translates to a voltage resolution
that is dependent on the range selected.
The resolution is given by
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, calculate the step
size as
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Data Sheet
Table 5. Voltage Range Limits
Voltage Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
6.0 to 14.4
VB (V)
0.573
1.25
2.5
6.0
VR (V)
0.802
1.75
3.5
8.4
The threshold value required is given by
VT = (VR × N)/255 + VB
where:
VT is the desired threshold voltage (undervoltage or overvoltage).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is given by
N = 255 × (VT VB)/VR
For example, if the user wants to set a 5 V overvoltage threshold
on VP1, the code to be programmed in the PS1OVTH register
is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
INPUT COMPARATOR HYSTERESIS
The undervoltage and overvoltage comparators shown in Figure 23
are always monitoring VPx. To avoid chatter (multiple transitions
when the input is very close to the set threshold level), these
comparators have digitally programmable hysteresis. The hysteresis
can be programmed up to the values shown in Table 6.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
the undervoltage threshold to which the input must rise before
an undervoltage fault is deasserted. Similarly, the user can program
the amount below the overvoltage threshold to which an input
must fall before an overvoltage fault is deasserted.
ULTRA
LOW
VPx
RANGE
SELECT
VREF
LOW
MID
OV
+ COMPARATOR
GLITCH
FILTER
+
UV FAULT TYPE
COMPARATOR SELECT
FAULT
OUTPUT
Figure 23. Supply Fault Detector Block
Rev. 0 | Page 16 of 71










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