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PDF ( 数据手册 , 数据表 ) 28F008

零件编号 28F008
描述 3 Volt Advanced Boot Block Flash Memory
制造商 Intel
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28F008 数据手册, 描述, 功能
3 Volt Advanced Boot Block Flash
Memory
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Preliminary Datasheet
Product Features
s Flexible SmartVoltage Technology
— 2.7 V–3.6 V Read/Program/Erase
— 12 V VPP Fast Production Programming
s 2.7 V or 1.65 V I/O Option
— Reduces Overall System Power
s High Performance
— 2.7 V–3.6 V: 70 ns Max Access Time
s Optimized Block Sizes
— Eight 8-KB Blocks for Data,Top or
Bottom Locations
— Up to One Hundred Twenty-Seven 64-
KB Blocks for Code
s Block Locking
— VCC-Level Control through WP#
s Low Power Consumption
— 9 mA Typical Read Current
s Absolute Hardware-Protection
— VPP = GND Option
— VCC Lockout Voltage
s Extended Temperature Operation
— –40 °C to +85 °C
s Automated Program and Block Erase
— Status Registers
s Intel® Flash Data Integrator Software
— Flash Memory Manager
— System Interrupt Manager
— Supports Parameter Storage, Streaming
Data (e.g., Voice)
s Extended Cycling Capability
— Minimum 100,000 Block Erase Cycles
Guaranteed
s Automatic Power Savings Feature
— Typical ICCS after Bus Inactivity
s Standard Surface Mount Packaging
— 48-Ball CSP Packages
— 40- and 48-Lead TSOP Packages
s Density and Footprint Upgradeable for
common package
— 4-, 8-, 16-, 32- and 64-Mbit Densities
s ETOX™ VII (0.18 µ) Flash Technology
— 28F160/320/640B3xC
— 4-, 8-, 16-, and 32-Mbit also exist on
ETOX™ V (0.4µ) and/or ETOX ™ VI
(0.25µ) Flash Technology
s x8 not recommended for new designs
s 4-Mbit density not recommended for new
designs
The 3 Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.18 µm
technology, represents a feature-rich solution at overall lower system cost. The 3 Volt Advanced
Boot Block flash memory products in x16 will be available in 48-lead TSOP and 48-ball CSP
packages. The x8 option of this product family will only be available in 40-lead TSOP and 48-
ball µBGA* packages. Additional information on this product family can be obtained by
accessing Intel’s website at: http://www.intel.com/design/flash.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290580-012
October 2000







28F008 pdf, 数据表
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.1 Product Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete
voltage supply pins: VCC for read operation, VCCQ for output swing, and VPP for program and
erase operation. All 3 Volt Advanced Boot Block flash memory products provide program/erase
capability at 2.7 V or 12 V (for fast production programming) and read with VCC at 2.7 V. Since
many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can
provide substantial power savings.
The 3 Volt Advanced Boot Block flash memory products are available in either x8 or x16 packages
in the following densities: (see Section 6.0, “Ordering Information” on page 34 for availability.)
4-Mbit (4,194,304-bit) flash memory organized as 256 Kwords of 16 bits each or 512 Kbytes
of 8-bits each
8-Mbit (8,388,608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024 Kbytes
of 8-bits each
16-Mbit (16,777,216-bit) flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
32-Mbit (33,554,432-bit) flash memory organized as 2048 Kwords of 16 bits each
64-Mbit (67,108,864-bit) flash memory organized as 4096 Kwords of 16 bits each
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix)
of the address map in order to accommodate different microprocessor protocols for kernel code
location. The upper two (or lower two) parameter blocks can be locked to provide complete code
security for system initialization code. Locking and unlocking is controlled by WP# (see Section
3.3, “Block Locking” on page 14 for details).
The Command User Interface (CUI) serves as the interface between the microprocessor or
microcontroller and the internal operation of the flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for program and erase
operations, including verification, thereby un-burdening the microprocessor or microcontroller.
The status register indicates the status of the WSM by signifying block erase or word program
completion and status.
The 3 Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings
(APS) feature which minimizes system current drain, allowing for very low power designs. This
mode is entered following the completion of a read cycle (approximately 300 ns later).
The RP# pin provides additional protection against unwanted command writes that may occur
during system reset and power-up/down sequences due to invalid system bus conditions (see
Section 3.6, “Power-Up/Down Operation” on page 16).
Section 3.0, “Principles of Operation” on page 7 gives detailed explanation of the different modes
of operation. Complete current and voltage specifications can be found in Section 4.4, “DC
Characteristics” on page 20. Refer to Section 4.5, “AC Characteristics —Read Operations” on
page 23 for read, program and erase performance specifications.
2 3UHOLPLQDU\







28F008 equivalent, schematic
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
When the device is in read array mode, four control signals control data output:
WE# must be logic high (VIH)
CE# must be logic low (VIL)
OE# must be logic low (VIL)
RP# must be logic high (VIH)
In addition, the address of the desired location must be applied to the address pins. If the device is
not in read array mode, as would be the case after a program or erase operation, the Read Array
command (FFH) must be written to the CUI before array reads can take place.
Table 4. Command Codes and Descriptions
Code
00, 01,
60, 2F,
C0, 98
FF
40
10
20
D0
B0
70
50
90
Device Mode
Description
Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the right to redefine these
codes for future functions.
Read Array
Program Set-Up
Alternate
Program Set-Up
Erase Set-Up
Erase Confirm
Program / Erase
Resume
Program / Erase
Suspend
Read Status
Register
Clear Status
Register
Read Identifier
Places the device in read array mode, such that array data will be output on the data pins.
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See Section 3.2.4.
(See 40H/Program Set-Up)
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”
(b) place the device into the read status register mode, and (c) wait for another command. See
Section 3.2.5.
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches, and begin erasing the block indicated on the address pins. During erase, the
device will only respond to the Read Status Register and Erase Suspend commands. The
device will output status register data when CE# or OE# is toggled.
If a program or erase operation was previously suspended, this command will resume that
operation
Issuing this command will begin to suspend the currently executing program/erase operation.
The status register will indicate when the operation has been successfully suspended by
setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM status bit
(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the WSM and the
remainder of the chip if it is driven to VIL. See Section 3.2.4.1 and Section 3.2.4.1.
This command places the device into read status register mode. Reading the device will output
the contents of the status register, regardless of the address presented to the device. The
device automatically enters this mode after a program or erase operation has been initiated.
See Section 3.2.3.
The WSM can set the block lock status (SR.1) , VPP status (SR.3), program status (SR.4), and
erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
Puts the device into the intelligent identifier read mode, so that reading the device will output
the manufacturer and device codes (A0 = 0 for manufacturer, A0 = 1 for device, all other
address inputs must be 0). See Section Section 3.2.2.
NOTE: See Appendix A for mode transition information.
10 3UHOLPLQDU\










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