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零件编号 | 74HCT4075-Q100 | ||
描述 | Triple 3-input OR gate | ||
制造商 | NXP Semiconductors | ||
LOGO | |||
1 Page
74HC4075-Q100;
74HCT4075-Q100
Triple 3-input OR gate
Rev. 1 — 22 May 2013
Product data sheet
1. General description
The 74HC4075-Q100; 74HCT4075-Q100 is a triple 3-input OR gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC4075-Q100: CMOS level
For 74HCT4075-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC4075D-Q100 40 C to +125 C
74HCT4075D-Q100
74HC4075PW-Q100 40 C to +125 C
74HCT4075PW-Q100
Name
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT108-1
SOT402-1
NXP Semiconductors
74HC4075-Q100; 74HCT4075-Q100
Triple 3-input OR gate
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
y
Z
14
D
pin 1 index
1
e
EA
X
c
HE
vM A
8
A2
A1
7
bp
wM
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT max. A1 A2 A3 bp
c D(1) E(1) e
HE
L
Lp
Q
v
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
inches
0.069
0.010
0.004
0.057
0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.244
0.228
0.041
0.039
0.016
0.028
0.024
0.01
w y Z (1)
0.25 0.1
0.7
0.3
0.01
0.004
0.028
0.012
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT108-1
IEC
076E06
REFERENCES
JEDEC
JEITA
MS-012
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 8. Package outline SOT108-1 (SO14)
74HC_HCT4075_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 May 2013
© NXP B.V. 2013. All rights reserved.
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页数 | 13 页 | ||
下载 | [ 74HCT4075-Q100.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
74HCT4075-Q100 | Triple 3-input OR gate | NXP Semiconductors |
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