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PDF ( 数据手册 , 数据表 ) 74HCT40105

零件编号 74HCT40105
描述 4-bit x 16-word FIFO register
制造商 NXP Semiconductors
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74HCT40105 数据手册, 描述, 功能
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Rev. 4 — 29 January 2016
Product data sheet
1. General description
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that
can store 16 4-bit words. It can handle input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop, which stores a marker bit. A
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in
that position. The control flip-flop detects the state of the preceding flip-flop and
communicates its own status to the succeeding flip-flop. When a control flip-flop is in the
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The
clock pulse transfers data from the preceding four data latches into its own four data
latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid
data ripples through to the output end. As a result, the status of the first control flip-flop
(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop
(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest
data is removed from the bottom of the data stack (output end), all data entered later will
automatically ripple toward the output. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Independent asynchronous inputs and outputs
Expandable in either direction
Reset capability
Status indicators on inputs and outputs
3-state outputs
Input levels:
For 74HC40105: CMOS level
For 74HCT40105: TTL level
3-state outputs
Complies with JEDEC standard JESD7A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C







74HCT40105 pdf, 数据表
NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
8. Recommended operating conditions
Table 4. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
9. Static characteristics
74HC40105
Min Typ Max
2.0 5.0 6.0
0 - VCC
0 - VCC
40 +25 +125
- - 625
- 1.67 139
- - 83
74HCT40105
Min Typ Max
4.5 5.0 5.5
0 - VCC
0 - VCC
40 +25 +125
---
- 1.67 139
---
Unit
V
V
V
C
ns/V
ns/V
ns/V
Table 5. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min
Max
74HC40105
VIH
HIGH-level
VCC = 2.0 V
input voltage VCC = 4.5 V
1.5 1.2 -
1.5
-
1.5
-V
3.15 2.4 - 3.15
-
3.15
-V
VCC = 6.0 V
4.2 3.2 -
4.2
-
4.2
-V
VIL LOW-level VCC = 2.0 V
input voltage VCC = 4.5 V
- 0.8 0.5
-
0.5
-
0.5 V
- 2.1 1.35 -
1.35
-
1.35 V
VCC = 6.0 V
- 2.8 1.8
-
1.8
-
1.8 V
VOH HIGH-level VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V 1.9 2.0
-
1.9
-
1.9
-V
IO = 20 A; VCC = 4.5 V 4.4 4.5 -
4.4
-
4.4
-V
IO = 20 A; VCC = 6.0 V 5.9 6.0 -
5.9
-
5.9
-V
IO = 4 mA; VCC = 4.5 V 3.98 4.32 -
3.84
-
3.7
-V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 -
5.34
-
5.2
-V
VOL LOW-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
- 0 0.1
-
0.1
-
0.1 V
IO = 20 A; VCC = 4.5 V
- 0 0.1
-
0.1
-
0.1 V
IO = 20 A; VCC = 6.0 V
- 0 0.1
-
0.1
-
0.1 V
IO = 4 mA; VCC = 4.5 V
- 0.15 0.26 -
0.33
-
0.4 V
IO = 5.2 mA; VCC = 6.0 V
- 0.15 0.26
-
0.33
-
0.4 V
II input leakage VI = VCC or GND;
current
VCC = 6.0 V
- - 0.1 -
1.0
-
1.0 A
IOZ OFF-state VI = VIH or VIL;
output current VO = VCC or GND;
VCC = 6.0 V
- - 0.5 - 5.0 - 10.0 A
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 36







74HCT40105 equivalent, schematic
NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
11.2 Shifting in sequence FIFO empty to FIFO full
6,LQSXW
',5RXWSXW
VWZRUG
IPD[
 90

W3+/
W:

90
 
QGZRUG
90

WKZRUG

'QLQSXW
DDD
Measurement points are given in Table 7.
VOL and VOH are typical voltage output levels that occur with the output load.
(1) DIR initially HIGH; FIFO is prepared for valid data
(2) SI set HIGH; data loaded into input stage
(3) DIR drops LOW; input stage “busy”
(4) DIR goes HIGH; status flag indicates FIFO prepared for additional data
(5) SI set LOW; data from first location “ripple through”
(6) To load 2nd word through to 16th word into FIFO, repeat the process.
(7) DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
Fig 8. Propagation delay SI input to DIR output, the SI pulse width and the SI maximum frequency
Table 7. Measurement points
Type
Input
74HC40105
74HCT40105
VM
0.5VCC
1.3 V
Output
VM
0.5VCC
1.3 V
VX
0.1VCC
0.1VCC
VY
0.9VCC
0.9VCC
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 36










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