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PDF ( 数据手册 , 数据表 ) ADF4218

零件编号 ADF4218
描述 Dual RF PLL Frequency Synthesizers
制造商 Analog Devices
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ADF4218 数据手册, 描述, 功能
a
Dual RF PLL Frequency Synthesizers
ADF4216/ADF4217/ADF4218
FEATURES
GENERAL DESCRIPTION
ADF4216: 550 MHz/1.2 GHz
The ADF4216/ADF4217/ADF4218 are dual frequency synthe-
ADF4217: 550 MHz/2.0 GHz
sizers that can be used to implement local oscillators (LOs) in
ADF4218: 550 MHz/2.5 GHz
the upconversion and downconversion sections of wireless
2.7 V to 5.5 V Power Supply
receivers and transmitters. They can provide the LO for both
Selectable Charge Pump Currents
the RF and IF sections. They consist of a low-noise digital PFD
Selectable Dual Modulus Prescaler
(Phase Frequency Detector), a precision charge pump, a pro-
IF: 8/9 or 16/17
RF: 32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
OBase Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
BWireless LANS
Communications Test Equipment
SOCATV Equipment
grammable reference divider, programmable A and B counters,
and a dual-modulus prescaler (P/P+1). The A (6-bit) and B
(11-bit) counters, in conjunction with the dual modulus prescaler
(P/P+1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizers are
used with an external loop filter and VCOs (Voltage Con-
trolled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.
LFUNCTIONAL BLOCK DIAGRAM
EVDD1 VDD2 VP1 VP2
TEN=BP+A
ADF4216/ADF4217/ADF4218
IFINA
IFINB
IF
PRESCALER
11-BIT IF
B-COUNTER
PHASE
COMPARATOR
CHARGE
PUMP
CPIF
6-BIT IF
A-COUNTER
IF
LOCK
DETECT
REFIN
CLOCK
DATA
LE
OSCILLATOR
22-BIT
DATA
REGISTER
SDOUT
RFINA
RFINB
N = BP + A
RF
PRESCALER
14-BIT IF
R-COUNTER
14-BIT IF
R-COUNTER
11-BIT RF
B-COUNTER
6-BIT RF
A-COUNTER
OUTPUT
MUX
MUXOUT
RF
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
CPRF
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DGNDRF AGNDRF DGNDIF DGNDIF AGNDIF
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000







ADF4218 pdf, 数据表
ADF4216/ADF4217/ADF4218
10dB/DIVISION
RL = 40dBc/Hz
RMS NOISE = 0.52؇
60 40
VDD = 3V
VP = 5V
50
60
70 0.60؇ rms
70
80
80 90
100
110
90
120
130
100
40
20
0 20 40 60
TEMPERATURE ؇C
80 100
TPC 13. ADF4218 RF Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
O5
B15 VDD = 3V
S25 VP= 5V
O35
45
L55
E65
TE75
140
100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
TPC 16. ADF4218 IF Integrated Phase Noise (540 MHz,
200 kHz, 20 kHz)
0
10
REFERENCE
LEVEL = 4.2dBm
VDD = 3V, VP = 5V
ICP = 5mA
20 PFD FREQUENCY = 200kHz
30 LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
40 VIDEO BANDWIDTH = 10Hz
50 SWEEP = 2.5 SECONDS
AVERAGES = 30
60
70
85 80 88.0dBc
95 90
105
0
1 234
TUNING VOLTAGE Volts
5
100
400kHz 200kHz
900MHz
+200kHz +400kHz
TPC 14. ADF4218 RF Reference Spurs vs. VTUNE (900 MHz,
200 kHz, 20 kHz)
TPC 17. ADF4218 IF Reference Spurs (540 MHz, 200 kHz,
20 kHz)
0
10 REFERENCE VDD = 3V, VP = 5V
LEVEL = 4.2dBm
ICP = 4.375mA
20 PFD FREQUENCY = 200kHz
30 LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
40 VIDEO BANDWIDTH = 10Hz
50 SWEEP = 1.9 SECONDS
AVERAGES = 19
60
70 89dBc/Hz
80
90
100
2kHz
1kHz
900MHz
+1kHz
+2kHz
TPC 15. ADF4218 IF Phase Noise (540 MHz, 200 kHz, 20 kHz)
120
130
VDD = 3V
VP = 5V
140
150
160
170
180
1
10 100 1000
PHASE DETECTOR FREQUENCY kHz
10000
TPC 18. ADF4218 IF Phase Noise vs. PFD Frequency
–8– REV. 0







ADF4218 equivalent, schematic
ADF4216/ADF4217/ADF4218
Table VI. RF AB Counter Latch Map
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
A6 A5 A4 A3 A2 A1 C2 (1) C1 (1)
OBSOLETEB11 B10 B9
A COUNTER
A6 A5 A4 A3 A2 A1 DIVIDE RATIO
XX0 0 0 0 0
XX0 0 0 1 1
XX0 0 1 0 2
XX0 0 1 1 3
......
......
......
X X 1 1 1 0 14
X X 1 1 1 1 15
B3 B2 B1 B COUNTER DIVIDE RATIO
0
0
0
..........
0
0
0
NOT ALLOWED
0
0
0
..........
0
0
1
NOT ALLOWED
0
0
0
..........
0
1
0
NOT ALLOWED
0
0
0
..........
0
1
1
3
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
2044
1
1
1
..........
1
0
1
2045
1
1
1
..........
1
1
0
2046
1
1
1
..........
1
1
1
2047
P14 RF PRESCALER
0 64/65
1 32/33
P16 RF SECTION
0 NORMAL OPERATION
1 POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE
GREATER THAN OR EQUAL TO A. FOR ENSURE CONTINUOUSLY
ADJACENT VALUES OF N, NMIN IS (P2 P).
–16–
REV. 0










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